Search

William Wicker

Examiner (ID: 8473)

Most Active Art Unit
3403
Art Unit(s)
3403, 3746, 2838
Total Applications
288
Issued Applications
242
Pending Applications
20
Abandoned Applications
26

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14523111 [patent_doc_number] => 10338815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Multi-channel nonvolatile memory power loss management [patent_app_type] => utility [patent_app_number] => 15/807855 [patent_app_country] => US [patent_app_date] => 2017-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5717 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15807855 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/807855
Multi-channel nonvolatile memory power loss management Nov 8, 2017 Issued
Array ( [id] => 14491565 [patent_doc_number] => 10332580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => DRAM and method for determining binary logic using a test voltage level [patent_app_type] => utility [patent_app_number] => 15/782271 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7375 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782271 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/782271
DRAM and method for determining binary logic using a test voltage level Oct 11, 2017 Issued
Array ( [id] => 12630990 [patent_doc_number] => 20180102160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => DDR Controller for Thyristor Memory Cell Arrays [patent_app_type] => utility [patent_app_number] => 15/729627 [patent_app_country] => US [patent_app_date] => 2017-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15729627 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/729627
DDR Controller for Thyristor Memory Cell Arrays Oct 9, 2017 Abandoned
Array ( [id] => 14135387 [patent_doc_number] => 20190102083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => MULTI-LEVEL CELL SOLID STATE DEVICE AND METHOD FOR STORING DATA TO PROVIDE CASCADED DATA PATH PERFORMANCE [patent_app_type] => utility [patent_app_number] => 15/722989 [patent_app_country] => US [patent_app_date] => 2017-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15722989 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/722989
Multi-level cell solid state device and method for transferring data between a host and the multi-level cell solid state device Oct 1, 2017 Issued
Array ( [id] => 16471774 [patent_doc_number] => 20200373312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => FERROELECTRIC CAPACITORS WITH BACKEND TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/636199 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16636199 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/636199
Ferroelectric capacitors with backend transistors Sep 28, 2017 Issued
Array ( [id] => 17652765 [patent_doc_number] => 11355505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Vertical backend transistor with ferroelectric material [patent_app_type] => utility [patent_app_number] => 16/640041 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9061 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16640041 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/640041
Vertical backend transistor with ferroelectric material Sep 28, 2017 Issued
Array ( [id] => 13392869 [patent_doc_number] => 20180247977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => ELECTRONIC MEMORY USING MEMRISTORS AND CROSSBARS [patent_app_type] => utility [patent_app_number] => 15/714329 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714329 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/714329
Electronic memory using memristors and crossbars activating a plurality of memristors in series Sep 24, 2017 Issued
Array ( [id] => 13361267 [patent_doc_number] => 20180232173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => HYBRID MEMORY SYSTEM AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/702499 [patent_app_country] => US [patent_app_date] => 2017-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15702499 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/702499
Hybrid memory system and refresh method thereof based on a read-to-write ratio of a page Sep 11, 2017 Issued
Array ( [id] => 12868453 [patent_doc_number] => 20180181326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/701656 [patent_app_country] => US [patent_app_date] => 2017-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12203 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15701656 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/701656
Memory system and method for operating the same for increasing a read reclaim count value Sep 11, 2017 Issued
Array ( [id] => 12691888 [patent_doc_number] => 20180122462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 15/699981 [patent_app_country] => US [patent_app_date] => 2017-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15699981 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/699981
Electronic device with a reference resistance adjustment block Sep 7, 2017 Issued
Array ( [id] => 13451349 [patent_doc_number] => 20180277217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/694843 [patent_app_country] => US [patent_app_date] => 2017-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15694843 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/694843
Semiconductor memory device for providing different voltages to grouped memory blocks Sep 2, 2017 Issued
Array ( [id] => 12778150 [patent_doc_number] => 20180151218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => METHOD OF OPERATING MEMORY DEVICE AND METHOD OF OPERATING MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 15/691828 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15691828 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/691828
Method of refreshing memory device and memory system based on storage capacity Aug 30, 2017 Issued
Array ( [id] => 14555263 [patent_doc_number] => 10346092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Apparatuses and methods for in-memory operations using timing circuitry [patent_app_type] => utility [patent_app_number] => 15/693390 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 15797 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693390 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/693390
Apparatuses and methods for in-memory operations using timing circuitry Aug 30, 2017 Issued
Array ( [id] => 15233703 [patent_doc_number] => 10504580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Systems and methods for refreshing a memory bank while accessing another memory bank using a shared address path [patent_app_type] => utility [patent_app_number] => 15/692804 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 13944 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15692804 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/692804
Systems and methods for refreshing a memory bank while accessing another memory bank using a shared address path Aug 30, 2017 Issued
Array ( [id] => 13995207 [patent_doc_number] => 20190066761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => PROCESSING IN MEMORY [patent_app_type] => utility [patent_app_number] => 15/693366 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693366 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/693366
Processing in memory device including a row address strobe manager Aug 30, 2017 Issued
Array ( [id] => 14671519 [patent_doc_number] => 10373674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Apparatuses and methods for data transmission offset values in burst transmissions [patent_app_type] => utility [patent_app_number] => 15/692937 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6949 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15692937 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/692937
Apparatuses and methods for data transmission offset values in burst transmissions Aug 30, 2017 Issued
Array ( [id] => 15109339 [patent_doc_number] => 10476002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Method for thermally treating semiconductor structure before saving data [patent_app_type] => utility [patent_app_number] => 15/690353 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5058 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690353 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690353
Method for thermally treating semiconductor structure before saving data Aug 29, 2017 Issued
Array ( [id] => 13708731 [patent_doc_number] => 20170365320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => VIRTUAL GROUND SENSING CIRCUITRY AND RELATED DEVICES, SYSTEMS, AND METHODS FOR CROSSPOINT FERROELECTRIC MEMORY [patent_app_type] => utility [patent_app_number] => 15/674050 [patent_app_country] => US [patent_app_date] => 2017-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15674050 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/674050
Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory Aug 9, 2017 Issued
Array ( [id] => 14332559 [patent_doc_number] => 10297303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory [patent_app_type] => utility [patent_app_number] => 15/674019 [patent_app_country] => US [patent_app_date] => 2017-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 16459 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15674019 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/674019
Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory Aug 9, 2017 Issued
Array ( [id] => 14298831 [patent_doc_number] => 10289542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Apparatuses and methods for memory device as a store for block program instructions [patent_app_type] => utility [patent_app_number] => 15/669590 [patent_app_country] => US [patent_app_date] => 2017-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11251 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15669590 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/669590
Apparatuses and methods for memory device as a store for block program instructions Aug 3, 2017 Issued
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