Willie L Davis

Array ( [id] => 17077734 [patent_doc_number] => 11114145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Three-dimensional magnetic device and magnetic memory [patent_app_type] => utility [patent_app_number] => 16/845593 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 4852 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16180153 [patent_doc_number] => 20200227122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => SEMICONDUCTOR MEMORY WITH DIFFERENT THRESHOLD VOLTAGES OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/832891 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 94746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16832891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16788982 [patent_doc_number] => 10991419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Semiconductor devices and methods of handling data lifetime codes used therein [patent_app_type] => utility [patent_app_number] => 16/828395 [patent_app_country] => US [patent_app_date] => 2020-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7646 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16828395 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17047801 [patent_doc_number] => 11100991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Apparatuses, devices and methods for sensing a snapback event in a circuit [patent_app_type] => utility [patent_app_number] => 16/825259 [patent_app_country] => US [patent_app_date] => 2020-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5745 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16825259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16653147 [patent_doc_number] => 10930338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Semiconductor device having PDA function [patent_app_type] => utility [patent_app_number] => 16/818425 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7710 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16818425 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16256537 [patent_doc_number] => 20200265912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => MODIFYING MEMORY BANK OPERATING PARAMETERS [patent_app_type] => utility [patent_app_number] => 16/805049 [patent_app_country] => US [patent_app_date] => 2020-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18587 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16805049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17055538 [patent_doc_number] => 20210264972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => VARYING-POLARITY READ OPERATIONS FOR POLARITY-WRITTEN MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/797432 [patent_app_country] => US [patent_app_date] => 2020-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16797432 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16819685 [patent_doc_number] => 11004522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Fail bit number counting circuit and non-volatile semiconductor storage device [patent_app_type] => utility [patent_app_number] => 16/796957 [patent_app_country] => US [patent_app_date] => 2020-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 7243 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17195863 [patent_doc_number] => 11164628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Compensating PCM drift for neuromorphic applications [patent_app_type] => utility [patent_app_number] => 16/797626 [patent_app_country] => US [patent_app_date] => 2020-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16797626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17152270 [patent_doc_number] => 11145357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Memory system, memory controller and method for operating memory system [patent_app_type] => utility [patent_app_number] => 16/796553 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17210484 [patent_doc_number] => 11170859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Memory device for passing verify operation and operating method of the same [patent_app_type] => utility [patent_app_number] => 16/796547 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 21769 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796547 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16937421 [patent_doc_number] => 20210203310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => LATCH CIRCUIT, MEMORY DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 16/796800 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796800 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16911228 [patent_doc_number] => 11043276 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-22 [patent_title] => Sense amplifier architecture providing improved memory performance [patent_app_type] => utility [patent_app_number] => 16/796270 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 16156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17486096 [patent_doc_number] => 20220093600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE INCLUDING THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/427934 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17427934 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16553132 [patent_doc_number] => 10886297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Semiconductor memory device including a laminated body with a plurality of semiconductor layers [patent_app_type] => utility [patent_app_number] => 16/785812 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 9552 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16785812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17002338 [patent_doc_number] => 11081160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Apparatus and methods for triggering row hammer address sampling [patent_app_type] => utility [patent_app_number] => 16/783063 [patent_app_country] => US [patent_app_date] => 2020-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7587 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16783063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16521436 [patent_doc_number] => 10872659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Memory system having write assist circuit including memory-adapted transistors [patent_app_type] => utility [patent_app_number] => 16/780739 [patent_app_country] => US [patent_app_date] => 2020-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 17986 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16780739 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17093118 [patent_doc_number] => 11121316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Symmetric tunable PCM resistor for artificial intelligence circuits [patent_app_type] => utility [patent_app_number] => 16/749042 [patent_app_country] => US [patent_app_date] => 2020-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4493 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16749042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16981207 [patent_doc_number] => 20210225444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => NON VOLATILE CROSS POINT MEMORY HAVING WORD LINE PASS TRANSISTOR WITH MULTIPLE ACTIVE STATES [patent_app_type] => utility [patent_app_number] => 16/748104 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16748104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15938519 [patent_doc_number] => 20200160893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => APPARATUSES AND METHOD FOR REDUCING ROW ADDRESS TO COLUMN ADDRESS DELAY FOR A VOLTAGE THRESHOLD COMPENSATION SENSE AMPLIFIER [patent_app_type] => utility [patent_app_number] => 16/747824 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7665 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747824 [rel_patent_id] =>[rel_patent_doc_number] =>)