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Willie L Davis

Examiner (ID: 16130)

Most Active Art Unit
2877
Art Unit(s)
2877
Total Applications
12
Issued Applications
10
Pending Applications
0
Abandoned Applications
2

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16979572 [patent_doc_number] => 20210223809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => ON-CHIP PARAMETER GENERATION SYSTEM WITH AN INTEGRATED CALIBRATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/748674 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12517 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16748674 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/748674
On-chip parameter generation system with an integrated calibration circuit Jan 20, 2020 Issued
Array ( [id] => 16574796 [patent_doc_number] => 10896721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Controller architecture for reducing on-die capacitance [patent_app_type] => utility [patent_app_number] => 16/746365 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746365 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/746365
Controller architecture for reducing on-die capacitance Jan 16, 2020 Issued
Array ( [id] => 15873741 [patent_doc_number] => 20200144274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => THREE-DIMENSIONAL MONOLITHIC VERTICAL TRANSISTOR MEMORY CELL WITH UNIFIED INTER-TIER CROSS-COUPLE [patent_app_type] => utility [patent_app_number] => 16/733772 [patent_app_country] => US [patent_app_date] => 2020-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16733772 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/733772
Three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple Jan 2, 2020 Issued
Array ( [id] => 16432668 [patent_doc_number] => 10832761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Polarization gate stack SRAM [patent_app_type] => utility [patent_app_number] => 16/732951 [patent_app_country] => US [patent_app_date] => 2020-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7553 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16732951 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/732951
Polarization gate stack SRAM Jan 1, 2020 Issued
Array ( [id] => 15745259 [patent_doc_number] => 20200111519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => SEMICONDUCTOR DEVICE VERIFYING SIGNAL SUPPLIED FROM OUTSIDE [patent_app_type] => utility [patent_app_number] => 16/709160 [patent_app_country] => US [patent_app_date] => 2019-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16709160 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/709160
Semiconductor device verifying signal supplied from outside Dec 9, 2019 Issued
Array ( [id] => 17152265 [patent_doc_number] => 11145352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Memory with adjustable TSV delay [patent_app_type] => utility [patent_app_number] => 16/706548 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7312 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16706548 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/706548
Memory with adjustable TSV delay Dec 5, 2019 Issued
Array ( [id] => 16958874 [patent_doc_number] => 11062751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 16/704320 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9284 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16704320 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/704320
Memory device Dec 4, 2019 Issued
Array ( [id] => 16888690 [patent_doc_number] => 20210174887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => NON-VOLATILE MEMORY WITH ERASE VERIFY SKIP [patent_app_type] => utility [patent_app_number] => 16/704428 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16599 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16704428 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/704428
Non-volatile memory with erase verify skip Dec 4, 2019 Issued
Array ( [id] => 16180152 [patent_doc_number] => 20200227121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => STORAGE CELL USING CHARGE-TRAPPING DEVICES [patent_app_type] => utility [patent_app_number] => 16/703892 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703892 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/703892
Storage cell using charge-trapping devices Dec 4, 2019 Issued
Array ( [id] => 17416801 [patent_doc_number] => 20220051705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => DRAM INTERFACE MODE WITH IMPROVED CHANNEL INTEGRITY AND EFFICIENCY AT HIGH SIGNALING RATES [patent_app_type] => utility [patent_app_number] => 17/299554 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17299554 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/299554
DRAM interface mode with improved channel integrity and efficiency at high signaling rates Dec 1, 2019 Issued
Array ( [id] => 16372187 [patent_doc_number] => 10803953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Memory system for restraining threshold variation to improve data reading [patent_app_type] => utility [patent_app_number] => 16/697540 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11392 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16697540 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/697540
Memory system for restraining threshold variation to improve data reading Nov 26, 2019 Issued
Array ( [id] => 16973412 [patent_doc_number] => 11069391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Dual-precision analog memory cell and array [patent_app_type] => utility [patent_app_number] => 16/693332 [patent_app_country] => US [patent_app_date] => 2019-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5217 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16693332 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/693332
Dual-precision analog memory cell and array Nov 23, 2019 Issued
Array ( [id] => 16447977 [patent_doc_number] => 10839908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Semiconductor memory device applying different voltages to respective select gate lines [patent_app_type] => utility [patent_app_number] => 16/692374 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 7118 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692374 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/692374
Semiconductor memory device applying different voltages to respective select gate lines Nov 21, 2019 Issued
Array ( [id] => 16944387 [patent_doc_number] => 11056640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Magnetoresistive memory device including a high dielectric constant capping layer and methods of making the same [patent_app_type] => utility [patent_app_number] => 16/693006 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 16133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16693006 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/693006
Magnetoresistive memory device including a high dielectric constant capping layer and methods of making the same Nov 21, 2019 Issued
Array ( [id] => 17353007 [patent_doc_number] => 11227651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Static random access memory read path with latch [patent_app_type] => utility [patent_app_number] => 16/692714 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 9909 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692714 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/692714
Static random access memory read path with latch Nov 21, 2019 Issued
Array ( [id] => 17137480 [patent_doc_number] => 11139045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-05 [patent_title] => Memory device with a memory repair mechanism and methods for operating the same [patent_app_type] => utility [patent_app_number] => 16/693126 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 11603 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16693126 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/693126
Memory device with a memory repair mechanism and methods for operating the same Nov 21, 2019 Issued
Array ( [id] => 16479330 [patent_doc_number] => 10854283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Memory device with enhanced access capability and associated method [patent_app_type] => utility [patent_app_number] => 16/689852 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8084 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689852 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/689852
Memory device with enhanced access capability and associated method Nov 19, 2019 Issued
Array ( [id] => 16911215 [patent_doc_number] => 11043263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-22 [patent_title] => Low offset and enhanced write margin for stacked fabric dies [patent_app_type] => utility [patent_app_number] => 16/683846 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4043 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16683846 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/683846
Low offset and enhanced write margin for stacked fabric dies Nov 13, 2019 Issued
Array ( [id] => 16880911 [patent_doc_number] => 11031067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Semiconductor memory device for securing sensing margin at cryogenic temperature [patent_app_type] => utility [patent_app_number] => 16/683926 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4521 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16683926 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/683926
Semiconductor memory device for securing sensing margin at cryogenic temperature Nov 13, 2019 Issued
Array ( [id] => 16637782 [patent_doc_number] => 10916296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/684564 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8929 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684564 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684564
Semiconductor structure and manufacturing method thereof Nov 13, 2019 Issued
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