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Willie L Davis

Examiner (ID: 16130)

Most Active Art Unit
2877
Art Unit(s)
2877
Total Applications
12
Issued Applications
10
Pending Applications
0
Abandoned Applications
2

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16738724 [patent_doc_number] => 10964385 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-30 [patent_title] => Restoring memory cell threshold voltages [patent_app_type] => utility [patent_app_number] => 16/684526 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 16959 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684526 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684526
Restoring memory cell threshold voltages Nov 13, 2019 Issued
Array ( [id] => 16827546 [patent_doc_number] => 20210142839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => Devices and Methods to Store an Initialization State [patent_app_type] => utility [patent_app_number] => 16/683192 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16683192 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/683192
Devices and methods to store an initialization state Nov 12, 2019 Issued
Array ( [id] => 15563875 [patent_doc_number] => 20200066349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/671692 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10941 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671692 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/671692
Semiconductor memory system including a plurality of semiconductor memory devices Oct 31, 2019 Issued
Array ( [id] => 16818566 [patent_doc_number] => 11003392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Memory controller and method of operating the memory controller [patent_app_type] => utility [patent_app_number] => 16/672087 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 18335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16672087 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/672087
Memory controller and method of operating the memory controller Oct 31, 2019 Issued
Array ( [id] => 15625651 [patent_doc_number] => 20200083230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => Integrated Assemblies Having Continuous High-Dielectric Films Extending Across Channel Regions of Adjacent Transistors [patent_app_type] => utility [patent_app_number] => 16/654172 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7714 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16654172 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/654172
Integrated assemblies having continuous high-dielectric films extending across channel regions of adjacent transistors Oct 15, 2019 Issued
Array ( [id] => 16372165 [patent_doc_number] => 10803931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Non-volatile memory having memory array with differential cells [patent_app_type] => utility [patent_app_number] => 16/581838 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 9136 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 563 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16581838 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/581838
Non-volatile memory having memory array with differential cells Sep 24, 2019 Issued
Array ( [id] => 15717111 [patent_doc_number] => 20200105323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => DATA RECEIVING CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/582322 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582322 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582322
Data receiving circuit Sep 24, 2019 Issued
Array ( [id] => 16819654 [patent_doc_number] => 11004491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Twisted wordline structures [patent_app_type] => utility [patent_app_number] => 16/582474 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4362 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582474 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582474
Twisted wordline structures Sep 24, 2019 Issued
Array ( [id] => 16723491 [patent_doc_number] => 20210090638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => PAGE BUFFER STRUCTURE AND FAST CONTINUOUS READ [patent_app_type] => utility [patent_app_number] => 16/581562 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8426 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16581562 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/581562
Page buffer structure and fast continuous read Sep 23, 2019 Issued
Array ( [id] => 16723534 [patent_doc_number] => 20210090681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => IMPRINT RECOVERY FOR MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/580972 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 65594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16580972 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/580972
Imprint recovery for memory cells Sep 23, 2019 Issued
Array ( [id] => 16803131 [patent_doc_number] => 10998082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Memory system for activating redundancy memory cell and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/568111 [patent_app_country] => US [patent_app_date] => 2019-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6106 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16568111 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/568111
Memory system for activating redundancy memory cell and operating method thereof Sep 10, 2019 Issued
Array ( [id] => 16372193 [patent_doc_number] => 10803959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Memory system including the semiconductor memory and a controller [patent_app_type] => utility [patent_app_number] => 16/563045 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 13309 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 472 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16563045 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/563045
Memory system including the semiconductor memory and a controller Sep 5, 2019 Issued
Array ( [id] => 16186882 [patent_doc_number] => 10720218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-21 [patent_title] => Nonvolatile memory device and an erase method thereof [patent_app_type] => utility [patent_app_number] => 16/563034 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 12683 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16563034 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/563034
Nonvolatile memory device and an erase method thereof Sep 5, 2019 Issued
Array ( [id] => 16653397 [patent_doc_number] => 10930590 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-23 [patent_title] => Interconnect device and method [patent_app_type] => utility [patent_app_number] => 16/549110 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9352 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549110 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/549110
Interconnect device and method Aug 22, 2019 Issued
Array ( [id] => 16707463 [patent_doc_number] => 10957405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Memory system configured to update write voltage applied to memory cells based on number of write or erase operations [patent_app_type] => utility [patent_app_number] => 16/548136 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14498 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16548136 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/548136
Memory system configured to update write voltage applied to memory cells based on number of write or erase operations Aug 21, 2019 Issued
Array ( [id] => 16431603 [patent_doc_number] => 10831685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Semiconductor memory systems with on-die data buffering [patent_app_type] => utility [patent_app_number] => 16/546694 [patent_app_country] => US [patent_app_date] => 2019-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 35 [patent_no_of_words] => 13107 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16546694 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/546694
Semiconductor memory systems with on-die data buffering Aug 20, 2019 Issued
Array ( [id] => 16660384 [patent_doc_number] => 20210057021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => APPARATUSES AND METHODS FOR ANALOG ROW ACCESS TRACKING [patent_app_type] => utility [patent_app_number] => 16/546152 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16546152 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/546152
Apparatuses and methods for analog row access tracking Aug 19, 2019 Issued
Array ( [id] => 16300840 [patent_doc_number] => 20200286563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/546112 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16546112 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/546112
Semiconductor memory device in which a conductive line connected to a word line selected for programming is charged to a voltage larger than the program voltage Aug 19, 2019 Issued
Array ( [id] => 16575313 [patent_doc_number] => 10897244 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-19 [patent_title] => Apparatuses and methods for voltage dependent delay [patent_app_type] => utility [patent_app_number] => 16/545384 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16545384 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/545384
Apparatuses and methods for voltage dependent delay Aug 19, 2019 Issued
Array ( [id] => 16645318 [patent_doc_number] => 10923182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Fixed-level charge sharing type LCV for memory compiler [patent_app_type] => utility [patent_app_number] => 16/545834 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16545834 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/545834
Fixed-level charge sharing type LCV for memory compiler Aug 19, 2019 Issued
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