Search

Willie L Davis

Examiner (ID: 16130)

Most Active Art Unit
2877
Art Unit(s)
2877
Total Applications
12
Issued Applications
10
Pending Applications
0
Abandoned Applications
2

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17144953 [patent_doc_number] => 20210312966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => SEMICONDUCTOR CIRCUIT AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/250649 [patent_app_country] => US [patent_app_date] => 2019-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17250649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/250649
Semiconductor circuit and electronic device for storing information Aug 7, 2019 Issued
Array ( [id] => 15563805 [patent_doc_number] => 20200066314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION [patent_app_type] => utility [patent_app_number] => 16/528523 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16528523 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/528523
Deferred fractional memory row activation Jul 30, 2019 Issued
Array ( [id] => 16386245 [patent_doc_number] => 10811086 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-20 [patent_title] => SRAM write yield enhancement with pull-up strength modulation [patent_app_type] => utility [patent_app_number] => 16/523350 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523350 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/523350
SRAM write yield enhancement with pull-up strength modulation Jul 25, 2019 Issued
Array ( [id] => 16601283 [patent_doc_number] => 20210027814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => DATA PROCESSING SYSTEM AND METHOD FOR GENERATING A DIGITAL CODE WITH A PHYSICALLY UNCLONABLE FUNCTION [patent_app_type] => utility [patent_app_number] => 16/523284 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523284 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/523284
Data processing system and method for generating a digital code with a physically unclonable function Jul 25, 2019 Issued
Array ( [id] => 16638181 [patent_doc_number] => 10916698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Semiconductor storage device including hexagonal insulating layer [patent_app_type] => utility [patent_app_number] => 16/523394 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4494 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523394 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/523394
Semiconductor storage device including hexagonal insulating layer Jul 25, 2019 Issued
Array ( [id] => 16187587 [patent_doc_number] => 10720932 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-21 [patent_title] => Digital to analog convertor, failure bit number detector and non-volatile semiconductor storage device [patent_app_type] => utility [patent_app_number] => 16/522684 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4284 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16522684 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/522684
Digital to analog convertor, failure bit number detector and non-volatile semiconductor storage device Jul 25, 2019 Issued
Array ( [id] => 15717127 [patent_doc_number] => 20200105331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => PURGEABLE MEMORY MAPPED FILES [patent_app_type] => utility [patent_app_number] => 16/522578 [patent_app_country] => US [patent_app_date] => 2019-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16522578 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/522578
Purgeable memory mapped files Jul 24, 2019 Issued
Array ( [id] => 16536311 [patent_doc_number] => 10878924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Data storage device intergrating host read commands and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/517171 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6895 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16517171 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/517171
Data storage device intergrating host read commands and method of operating the same Jul 18, 2019 Issued
Array ( [id] => 16356214 [patent_doc_number] => 10796731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Providing power availability information to memory [patent_app_type] => utility [patent_app_number] => 16/513115 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5918 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513115 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513115
Providing power availability information to memory Jul 15, 2019 Issued
Array ( [id] => 16502259 [patent_doc_number] => 10867652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-15 [patent_title] => Read circuit for magnetic tunnel junction (MTJ) memory [patent_app_type] => utility [patent_app_number] => 16/502430 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502430 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/502430
Read circuit for magnetic tunnel junction (MTJ) memory Jul 2, 2019 Issued
Array ( [id] => 15029931 [patent_doc_number] => 20190325970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => MEMORY SYSTEM PERFORMING READ OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/502302 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502302 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/502302
Memory system performing read of nonvolatile semiconductor memory device Jul 2, 2019 Issued
Array ( [id] => 16479343 [patent_doc_number] => 10854296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Semiconductor device and programming method of the semiconductor device [patent_app_type] => utility [patent_app_number] => 16/502392 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 8385 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502392 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/502392
Semiconductor device and programming method of the semiconductor device Jul 2, 2019 Issued
Array ( [id] => 16301821 [patent_doc_number] => 20200287544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => FAIL REDUNDANCY CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/460270 [patent_app_country] => US [patent_app_date] => 2019-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16460270 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/460270
Fail redundancy circuits Jul 1, 2019 Issued
Array ( [id] => 14969105 [patent_doc_number] => 20190312031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => ROM Chip Manufacturing Structures Having Shared Gate Electrodes [patent_app_type] => utility [patent_app_number] => 16/443276 [patent_app_country] => US [patent_app_date] => 2019-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6454 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16443276 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/443276
ROM chip manufacturing structures having shared gate electrodes Jun 16, 2019 Issued
Array ( [id] => 14968551 [patent_doc_number] => 20190311754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => Initialization Process for Magnetic Random Access Memory (MRAM) Production [patent_app_type] => utility [patent_app_number] => 16/442737 [patent_app_country] => US [patent_app_date] => 2019-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16442737 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/442737
Initialization process for magnetic random access memory (MRAM) production Jun 16, 2019 Issued
Array ( [id] => 14901193 [patent_doc_number] => 20190294362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => MEMORY DEVICE, A MEMORY CONTROLLER, A STORAGE DEVICE INCLUDING THE MEMORY DEVICE AND THE MEMORY CONTROLLER AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/439401 [patent_app_country] => US [patent_app_date] => 2019-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16439401 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/439401
Memory device, a memory controller, a storage device including the memory device and the memory controller and operating method thereof Jun 11, 2019 Issued
Array ( [id] => 15954789 [patent_doc_number] => 10665307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Memory devices configured to perform leak checks [patent_app_type] => utility [patent_app_number] => 16/432059 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8291 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432059 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/432059
Memory devices configured to perform leak checks Jun 4, 2019 Issued
Array ( [id] => 14842627 [patent_doc_number] => 20190279714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => Memory Systems and Memory Programming Methods [patent_app_type] => utility [patent_app_number] => 16/427229 [patent_app_country] => US [patent_app_date] => 2019-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5565 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16427229 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/427229
Memory systems and memory programming methods May 29, 2019 Issued
Array ( [id] => 16307361 [patent_doc_number] => 10776153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Information processing device and system capable of preventing loss of user data [patent_app_type] => utility [patent_app_number] => 16/387127 [patent_app_country] => US [patent_app_date] => 2019-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14459 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16387127 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/387127
Information processing device and system capable of preventing loss of user data Apr 16, 2019 Issued
Array ( [id] => 15580143 [patent_doc_number] => 10580463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Power supply wiring in a semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/380912 [patent_app_country] => US [patent_app_date] => 2019-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16380912 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/380912
Power supply wiring in a semiconductor memory device Apr 9, 2019 Issued
Menu