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Willie L Davis

Examiner (ID: 16130)

Most Active Art Unit
2877
Art Unit(s)
2877
Total Applications
12
Issued Applications
10
Pending Applications
0
Abandoned Applications
2

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14706633 [patent_doc_number] => 10381074 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-13 [patent_title] => Differential weight reading of an analog memory element in crosspoint array utilizing current subtraction transistors [patent_app_type] => utility [patent_app_number] => 15/949564 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5123 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949564 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/949564
Differential weight reading of an analog memory element in crosspoint array utilizing current subtraction transistors Apr 9, 2018 Issued
Array ( [id] => 15474785 [patent_doc_number] => 10553275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Device having write assist circuit including memory-adapted transistors and method for making the same [patent_app_type] => utility [patent_app_number] => 15/949774 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 16910 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949774 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/949774
Device having write assist circuit including memory-adapted transistors and method for making the same Apr 9, 2018 Issued
Array ( [id] => 15519461 [patent_doc_number] => 10566329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Semiconductor device having data signal path of meandering shape via a plurality of wirings [patent_app_type] => utility [patent_app_number] => 15/925762 [patent_app_country] => US [patent_app_date] => 2018-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6640 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15925762 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/925762
Semiconductor device having data signal path of meandering shape via a plurality of wirings Mar 18, 2018 Issued
Array ( [id] => 14078905 [patent_doc_number] => 20190088340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 15/916472 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916472 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/916472
Memory system including the semiconductor memory and a controller Mar 8, 2018 Issued
Array ( [id] => 15315035 [patent_doc_number] => 10522227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Semiconductor memory device applying different voltages to respective select gate lines [patent_app_type] => utility [patent_app_number] => 15/916404 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 7104 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916404 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/916404
Semiconductor memory device applying different voltages to respective select gate lines Mar 8, 2018 Issued
Array ( [id] => 14078891 [patent_doc_number] => 20190088333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 15/916538 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916538 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/916538
Memory system for restraining threshold variation to improve data reading Mar 8, 2018 Issued
Array ( [id] => 16210559 [patent_doc_number] => 20200243549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => FERROELECTRIC MEMORY IC AS WELL AS METHOD OF OPERATING THE SAME AND METHOD OF PREPARING THE SAME [patent_app_type] => utility [patent_app_number] => 16/322032 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16322032 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/322032
Ferroelectric memory IC as well as method of operating the same and method of preparing the same Feb 27, 2018 Issued
Array ( [id] => 16210559 [patent_doc_number] => 20200243549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => FERROELECTRIC MEMORY IC AS WELL AS METHOD OF OPERATING THE SAME AND METHOD OF PREPARING THE SAME [patent_app_type] => utility [patent_app_number] => 16/322032 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16322032 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/322032
Ferroelectric memory IC as well as method of operating the same and method of preparing the same Feb 27, 2018 Issued
Array ( [id] => 13995159 [patent_doc_number] => 20190066737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/906592 [patent_app_country] => US [patent_app_date] => 2018-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15906592 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/906592
Semiconductor memory device Feb 26, 2018 Issued
Array ( [id] => 14706593 [patent_doc_number] => 10381054 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-13 [patent_title] => Common boosted assist [patent_app_type] => utility [patent_app_number] => 15/906588 [patent_app_country] => US [patent_app_date] => 2018-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6745 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15906588 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/906588
Common boosted assist Feb 26, 2018 Issued
Array ( [id] => 15400721 [patent_doc_number] => 10541020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Controller architecture for reducing on-die capacitance [patent_app_type] => utility [patent_app_number] => 15/906998 [patent_app_country] => US [patent_app_date] => 2018-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3370 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15906998 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/906998
Controller architecture for reducing on-die capacitance Feb 26, 2018 Issued
Array ( [id] => 12871813 [patent_doc_number] => 20180182446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => SEMICONDUCTOR DEVICE VERIFYING SIGNAL SUPPLIED FROM OUTSIDE [patent_app_type] => utility [patent_app_number] => 15/903666 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15903666 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/903666
SEMICONDUCTOR DEVICE VERIFYING SIGNAL SUPPLIED FROM OUTSIDE Feb 22, 2018 Abandoned
Array ( [id] => 12849559 [patent_doc_number] => 20180175026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => ROM Chip Manufacturing Structures [patent_app_type] => utility [patent_app_number] => 15/894138 [patent_app_country] => US [patent_app_date] => 2018-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6423 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15894138 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/894138
ROM chip manufacturing structures having shared gate electrodes Feb 11, 2018 Issued
Array ( [id] => 13419447 [patent_doc_number] => 20180261266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION [patent_app_type] => utility [patent_app_number] => 15/889191 [patent_app_country] => US [patent_app_date] => 2018-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15889191 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/889191
Memory with deferred fractional row activation Feb 4, 2018 Issued
Array ( [id] => 15138977 [patent_doc_number] => 10482970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Semiconductor memory system including a plurality of semiconductor memory devices [patent_app_type] => utility [patent_app_number] => 15/881265 [patent_app_country] => US [patent_app_date] => 2018-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 31 [patent_no_of_words] => 10956 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881265 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/881265
Semiconductor memory system including a plurality of semiconductor memory devices Jan 25, 2018 Issued
Array ( [id] => 15153839 [patent_doc_number] => 20190355397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/475906 [patent_app_country] => US [patent_app_date] => 2018-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 393 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16475906 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/475906
Semiconductor device with reduced power consumption and operation method thereof, electronic component, and electronic device Jan 8, 2018 Issued
Array ( [id] => 13363283 [patent_doc_number] => 20180233181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/845698 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845698 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845698
Semiconductor device Dec 17, 2017 Issued
Array ( [id] => 14616561 [patent_doc_number] => 10360984 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Data storage device and method of operating the same [patent_app_type] => utility [patent_app_number] => 15/845406 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6877 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845406 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845406
Data storage device and method of operating the same Dec 17, 2017 Issued
Array ( [id] => 13542761 [patent_doc_number] => 20180322927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => Memory Array and Method for Reading, Programming and Erasing the Same [patent_app_type] => utility [patent_app_number] => 15/844806 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15844806 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/844806
Memory array and method for reading, programming and erasing the same Dec 17, 2017 Issued
Array ( [id] => 14888601 [patent_doc_number] => 10424347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Providing power availability information to memory [patent_app_type] => utility [patent_app_number] => 15/843195 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15843195 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/843195
Providing power availability information to memory Dec 14, 2017 Issued
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