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Willie L Davis

Examiner (ID: 16130)

Most Active Art Unit
2877
Art Unit(s)
2877
Total Applications
12
Issued Applications
10
Pending Applications
0
Abandoned Applications
2

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18874397 [patent_doc_number] => 11862218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Read circuit for magnetic tunnel junction (MTJ) memory [patent_app_type] => utility [patent_app_number] => 17/748560 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7362 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748560 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/748560
Read circuit for magnetic tunnel junction (MTJ) memory May 18, 2022 Issued
Array ( [id] => 18865576 [patent_doc_number] => 20230420013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => METHOD OF STORING DATA IN MEMORIES [patent_app_type] => utility [patent_app_number] => 17/747318 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11807 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747318 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747318
Method of storing data in memories May 17, 2022 Issued
Array ( [id] => 18439694 [patent_doc_number] => 20230186989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/746375 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10170 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746375 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/746375
MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE May 16, 2022 Pending
Array ( [id] => 18735519 [patent_doc_number] => 11804260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Multiplexors under an array of memory cells [patent_app_type] => utility [patent_app_number] => 17/746542 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7221 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746542 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/746542
Multiplexors under an array of memory cells May 16, 2022 Issued
Array ( [id] => 17840479 [patent_doc_number] => 20220277785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => COLUMN SELECT SIGNAL CELL CIRCUIT, BIT LINE SENSE CIRCUIT AND MEMORY [patent_app_type] => utility [patent_app_number] => 17/743497 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9797 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743497 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/743497
COLUMN SELECT SIGNAL CELL CIRCUIT, BIT LINE SENSE CIRCUIT AND MEMORY May 12, 2022 Pending
Array ( [id] => 18757223 [patent_doc_number] => 20230360681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => PULSE BASED MULTI-LEVEL CELL PROGRAMMING [patent_app_type] => utility [patent_app_number] => 17/740069 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17740069 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/740069
Pulse based multi-level cell programming May 8, 2022 Issued
Array ( [id] => 17810618 [patent_doc_number] => 20220262453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/735881 [patent_app_country] => US [patent_app_date] => 2022-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735881 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/735881
Memory device for selectively operating multiple memory groups in different speeds and memory system including the same May 2, 2022 Issued
Array ( [id] => 17810619 [patent_doc_number] => 20220262454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/735889 [patent_app_country] => US [patent_app_date] => 2022-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735889 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/735889
Memory device for selectively operating multiple memory groups in different speeds and memory system including the same May 2, 2022 Issued
Array ( [id] => 17810617 [patent_doc_number] => 20220262452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/735860 [patent_app_country] => US [patent_app_date] => 2022-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735860 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/735860
Memory device and memory system capable of using redundancy memory cells May 2, 2022 Issued
Array ( [id] => 17810608 [patent_doc_number] => 20220262443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => SEMICONDUCTOR MEMORY WITH DIFFERENT THRESHOLD VOLTAGES OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/735196 [patent_app_country] => US [patent_app_date] => 2022-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 94759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735196 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/735196
Semiconductor memory with different threshold voltages of memory cells May 2, 2022 Issued
Array ( [id] => 18729077 [patent_doc_number] => 20230343372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => AREA-EFFICIENT CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/725564 [patent_app_country] => US [patent_app_date] => 2022-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725564 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/725564
Area-efficient configuration latch for programmable logic device Apr 20, 2022 Issued
Array ( [id] => 17764531 [patent_doc_number] => 20220238144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => Systems and Methods for Controlling Power Management Operations in a Memory Device [patent_app_type] => utility [patent_app_number] => 17/722453 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722453 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/722453
Systems and methods for controlling power management operations in a memory device Apr 17, 2022 Issued
Array ( [id] => 18165230 [patent_doc_number] => 20230031828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => Memory device, memory test circuit and memory test method thereof having repair information maintaining mechanism [patent_app_type] => utility [patent_app_number] => 17/718356 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718356 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718356
Memory device, memory test circuit and memory test method thereof having repair information maintaining mechanism Apr 11, 2022 Issued
Array ( [id] => 18839990 [patent_doc_number] => 11848069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Page buffer including latches and memory device including the page buffer [patent_app_type] => utility [patent_app_number] => 17/718070 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 10417 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718070 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718070
Page buffer including latches and memory device including the page buffer Apr 10, 2022 Issued
Array ( [id] => 18696063 [patent_doc_number] => 20230326494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => NON-DESTRUCTIVE PATTERN IDENTIFICATION AT A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/716580 [patent_app_country] => US [patent_app_date] => 2022-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17716580 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/716580
Non-destructive pattern identification at a memory device Apr 7, 2022 Issued
Array ( [id] => 18679504 [patent_doc_number] => 20230317160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => MEMORY SYSTEM WITH PHYSICAL UNCLONABLE FUNCTION [patent_app_type] => utility [patent_app_number] => 17/710442 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710442 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/710442
Memory system with physical unclonable function Mar 30, 2022 Issued
Array ( [id] => 18307907 [patent_doc_number] => 20230111807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => LATCH CIRCUIT, TRANSMISSION CIRCUIT INCLUDING LATCH CIRCUIT, AND SEMICONDUCTOR APPARATUS INCLUDING TRANSMISSION CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/703646 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703646 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/703646
Latch circuit, transmission circuit including latch circuit, and semiconductor apparatus including transmission circuit Mar 23, 2022 Issued
Array ( [id] => 18998924 [patent_doc_number] => 11915778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Semiconductor memory device outputting data from memory cell groups in parallel and system [patent_app_type] => utility [patent_app_number] => 17/654890 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 21452 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654890 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654890
Semiconductor memory device outputting data from memory cell groups in parallel and system Mar 14, 2022 Issued
Array ( [id] => 18766738 [patent_doc_number] => 11817145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Programming multi-level memory cells [patent_app_type] => utility [patent_app_number] => 17/691684 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 20387 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17691684 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/691684
Programming multi-level memory cells Mar 9, 2022 Issued
Array ( [id] => 17660441 [patent_doc_number] => 20220180906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => DATA SORTING CONTROL CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/678488 [patent_app_country] => US [patent_app_date] => 2022-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17678488 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/678488
Data sorting control circuit and memory device including the same Feb 22, 2022 Issued
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