Search

Willie L Davis

Examiner (ID: 5098)

Most Active Art Unit
2877
Art Unit(s)
2877
Total Applications
12
Issued Applications
10
Pending Applications
0
Abandoned Applications
2

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6583464 [patent_doc_number] => 20100129991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'NITRIDE SEMICONDUCTOR DEVICE HAVING A SILICON-CONTAINING LAYER AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/641421 [patent_app_country] => US [patent_app_date] => 2009-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4168 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20100129991.pdf [firstpage_image] =>[orig_patent_app_number] => 12641421 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/641421
Nitride semiconductor device having a silicon-containing layer and manufacturing method thereof Dec 17, 2009 Issued
Array ( [id] => 8675883 [patent_doc_number] => 08383997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Heated planar element and method for its attachment' [patent_app_type] => utility [patent_app_number] => 12/640703 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 19833 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12640703 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/640703
Heated planar element and method for its attachment Dec 16, 2009 Issued
Array ( [id] => 9389959 [patent_doc_number] => 08686563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'Methods of forming fine patterns in the fabrication of semiconductor devices' [patent_app_type] => utility [patent_app_number] => 12/639542 [patent_app_country] => US [patent_app_date] => 2009-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 6138 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12639542 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/639542
Methods of forming fine patterns in the fabrication of semiconductor devices Dec 15, 2009 Issued
Array ( [id] => 6487229 [patent_doc_number] => 20100093132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'CHIP MODULE FOR COMPLETE POWER TRAIN' [patent_app_type] => utility [patent_app_number] => 12/637496 [patent_app_country] => US [patent_app_date] => 2009-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4227 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20100093132.pdf [firstpage_image] =>[orig_patent_app_number] => 12637496 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/637496
Chip module for complete power train Dec 13, 2009 Issued
Array ( [id] => 4577951 [patent_doc_number] => 07833842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'Mixed-scale electronic interface' [patent_app_type] => utility [patent_app_number] => 12/630076 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 52 [patent_no_of_words] => 9482 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/833/07833842.pdf [firstpage_image] =>[orig_patent_app_number] => 12630076 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/630076
Mixed-scale electronic interface Dec 2, 2009 Issued
Array ( [id] => 8701936 [patent_doc_number] => 08395159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Semiconductor apparatus with thin semiconductor film' [patent_app_type] => utility [patent_app_number] => 12/591475 [patent_app_country] => US [patent_app_date] => 2009-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 52 [patent_no_of_words] => 12454 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12591475 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/591475
Semiconductor apparatus with thin semiconductor film Nov 19, 2009 Issued
Array ( [id] => 7577244 [patent_doc_number] => 20110291126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/147830 [patent_app_country] => US [patent_app_date] => 2009-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10263 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20110291126.pdf [firstpage_image] =>[orig_patent_app_number] => 13147830 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/147830
Active matrix substrate and display device Nov 12, 2009 Issued
Array ( [id] => 7666728 [patent_doc_number] => 20110315997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'GaN Substrate and Method of Its Manufacture, Method of Manufacturing GaN Layer-Bonded Substrate, and Method of Manufacturing Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 13/147806 [patent_app_country] => US [patent_app_date] => 2009-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9693 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13147806 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/147806
GaN Substrate and Method of Its Manufacture, Method of Manufacturing GaN Layer-Bonded Substrate, and Method of Manufacturing Semiconductor Device Nov 12, 2009 Abandoned
Array ( [id] => 6271924 [patent_doc_number] => 20100117133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'MOS VARACTORS WITH LARGE TUNING RANGE' [patent_app_type] => utility [patent_app_number] => 12/616150 [patent_app_country] => US [patent_app_date] => 2009-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4005 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20100117133.pdf [firstpage_image] =>[orig_patent_app_number] => 12616150 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/616150
MOS varactors with large tuning range Nov 10, 2009 Issued
Array ( [id] => 7545305 [patent_doc_number] => 08053276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages' [patent_app_type] => utility [patent_app_number] => 12/614981 [patent_app_country] => US [patent_app_date] => 2009-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 6141 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/053/08053276.pdf [firstpage_image] =>[orig_patent_app_number] => 12614981 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/614981
Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages Nov 8, 2009 Issued
Array ( [id] => 7751389 [patent_doc_number] => 08110439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages' [patent_app_type] => utility [patent_app_number] => 12/614998 [patent_app_country] => US [patent_app_date] => 2009-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 6150 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/110/08110439.pdf [firstpage_image] =>[orig_patent_app_number] => 12614998 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/614998
Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages Nov 8, 2009 Issued
Array ( [id] => 6493942 [patent_doc_number] => 20100259865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'FILM CAPACITORS WITH IMPROVED DIELECTRIC STRENGTH BREAKDOWN' [patent_app_type] => utility [patent_app_number] => 12/614892 [patent_app_country] => US [patent_app_date] => 2009-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2974 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20100259865.pdf [firstpage_image] =>[orig_patent_app_number] => 12614892 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/614892
FILM CAPACITORS WITH IMPROVED DIELECTRIC STRENGTH BREAKDOWN Nov 8, 2009 Abandoned
Array ( [id] => 6516449 [patent_doc_number] => 20100122979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'Heating resistor element component' [patent_app_type] => utility [patent_app_number] => 12/589594 [patent_app_country] => US [patent_app_date] => 2009-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4132 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20100122979.pdf [firstpage_image] =>[orig_patent_app_number] => 12589594 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/589594
Heating resistor element component and method of manufacturing heating resistor element component Oct 25, 2009 Issued
Array ( [id] => 9184359 [patent_doc_number] => 08624297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Multi-layer circuit substrate fabrication and design methods providing improved transmission line integrity and increased routing density' [patent_app_type] => utility [patent_app_number] => 12/579517 [patent_app_country] => US [patent_app_date] => 2009-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3028 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12579517 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/579517
Multi-layer circuit substrate fabrication and design methods providing improved transmission line integrity and increased routing density Oct 14, 2009 Issued
Array ( [id] => 6255104 [patent_doc_number] => 20100029048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'Field Effect Semiconductor Diodes and Processing Techniques' [patent_app_type] => utility [patent_app_number] => 12/578443 [patent_app_country] => US [patent_app_date] => 2009-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3185 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20100029048.pdf [firstpage_image] =>[orig_patent_app_number] => 12578443 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/578443
Field Effect Semiconductor Diodes and Processing Techniques Oct 12, 2009 Abandoned
Array ( [id] => 8364127 [patent_doc_number] => 08253186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Semiconductor device having controllable transistor threshold voltage' [patent_app_type] => utility [patent_app_number] => 12/575915 [patent_app_country] => US [patent_app_date] => 2009-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 127 [patent_no_of_words] => 22444 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12575915 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/575915
Semiconductor device having controllable transistor threshold voltage Oct 7, 2009 Issued
Array ( [id] => 8653402 [patent_doc_number] => 08373151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-12 [patent_title] => 'Write-once memory array including phase-change elements and threshold switch isolation' [patent_app_type] => utility [patent_app_number] => 12/565224 [patent_app_country] => US [patent_app_date] => 2009-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3627 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12565224 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/565224
Write-once memory array including phase-change elements and threshold switch isolation Sep 22, 2009 Issued
Array ( [id] => 6489911 [patent_doc_number] => 20100009522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'Method for Forming Chalcogenide Switch with Crystallized Thin Film Diode Isolation' [patent_app_type] => utility [patent_app_number] => 12/564386 [patent_app_country] => US [patent_app_date] => 2009-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3618 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20100009522.pdf [firstpage_image] =>[orig_patent_app_number] => 12564386 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/564386
Method for forming chalcogenide switch with crystallized thin film diode isolation Sep 21, 2009 Issued
Array ( [id] => 6591788 [patent_doc_number] => 20100001393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/559941 [patent_app_country] => US [patent_app_date] => 2009-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6861 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20100001393.pdf [firstpage_image] =>[orig_patent_app_number] => 12559941 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/559941
Semiconductor device Sep 14, 2009 Issued
Array ( [id] => 8317421 [patent_doc_number] => 08232197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Method of manufacturing a semiconductor device from which damage layers and native oxide films in connection holes have been removed' [patent_app_type] => utility [patent_app_number] => 12/585238 [patent_app_country] => US [patent_app_date] => 2009-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3813 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12585238 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/585238
Method of manufacturing a semiconductor device from which damage layers and native oxide films in connection holes have been removed Sep 8, 2009 Issued
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