Search

Willis Little

Examiner (ID: 2267)

Most Active Art Unit
3203
Art Unit(s)
2103, 2401, 3203, 2403, 2107, 2406, 2899, 3616, 3643
Total Applications
2327
Issued Applications
2182
Pending Applications
48
Abandoned Applications
97

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19444551 [patent_doc_number] => 12094842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Semiconductor device having an antenna arranged over an active main surface of a semiconductor die [patent_app_type] => utility [patent_app_number] => 16/360387 [patent_app_country] => US [patent_app_date] => 2019-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 7910 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16360387 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/360387
Semiconductor device having an antenna arranged over an active main surface of a semiconductor die Mar 20, 2019 Issued
Array ( [id] => 15776565 [patent_doc_number] => 20200119300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => ELECTROLUMINESCENT DEVICE AND METHOD FOR FABRICATING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/620849 [patent_app_country] => US [patent_app_date] => 2019-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16620849 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/620849
Electroluminescent device comprising a target film comprising a small molecular layer and a large molecular layer and method for fabricating the same, display panel and display device Mar 7, 2019 Issued
Array ( [id] => 14722575 [patent_doc_number] => 20190252351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE HAVING AN ANTENNA PATTERN ELECTRICALLY COUPLED TO A FIRST REDISTRIBUTION LAYER (RDL) [patent_app_type] => utility [patent_app_number] => 16/279925 [patent_app_country] => US [patent_app_date] => 2019-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4959 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16279925 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/279925
SEMICONDUCTOR PACKAGE STRUCTURE HAVING AN ANTENNA PATTERN ELECTRICALLY COUPLED TO A FIRST REDISTRIBUTION LAYER (RDL) Feb 18, 2019 Abandoned
Array ( [id] => 16180707 [patent_doc_number] => 20200227676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => ORGANIC LIGHT-EMITTING DIODE DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/348153 [patent_app_country] => US [patent_app_date] => 2019-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16348153 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/348153
ORGANIC LIGHT-EMITTING DIODE DISPLAY DEVICE Jan 31, 2019 Abandoned
Array ( [id] => 18105522 [patent_doc_number] => 11545419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Semiconductor package having an additional material with a comparative tracking index (CTI) higher than that of encapsulant resin material formed between two terminals [patent_app_type] => utility [patent_app_number] => 16/239796 [patent_app_country] => US [patent_app_date] => 2019-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 11341 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 779 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239796 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/239796
Semiconductor package having an additional material with a comparative tracking index (CTI) higher than that of encapsulant resin material formed between two terminals Jan 3, 2019 Issued
Array ( [id] => 16440535 [patent_doc_number] => 20200357862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => PIXEL ARRANGEMENT, MANUFACTURING METHOD THEREOF, DISPLAY PANEL, DISPLAY DEVICE AND MASK [patent_app_type] => utility [patent_app_number] => 16/345979 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7884 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16345979 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/345979
PIXEL ARRANGEMENT, MANUFACTURING METHOD THEREOF, DISPLAY PANEL, DISPLAY DEVICE AND MASK Dec 18, 2018 Abandoned
Array ( [id] => 14191289 [patent_doc_number] => 20190115350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => THYRISTOR RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 16/217064 [patent_app_country] => US [patent_app_date] => 2018-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16217064 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/217064
Methods of forming a thyristor-based random access memory using fin structures and elevated layers Dec 11, 2018 Issued
Array ( [id] => 16560562 [patent_doc_number] => 20210005711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => VERTICAL POWER TRANSISTOR HAVING HETEROJUNCTIONS [patent_app_type] => utility [patent_app_number] => 16/767978 [patent_app_country] => US [patent_app_date] => 2018-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16767978 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/767978
VERTICAL POWER TRANSISTOR HAVING HETEROJUNCTIONS Nov 18, 2018 Abandoned
Array ( [id] => 16873737 [patent_doc_number] => 20210167204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => SEMICONDUCTOR DEVICE AND POWER CONVERTER [patent_app_type] => utility [patent_app_number] => 17/269254 [patent_app_country] => US [patent_app_date] => 2018-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17269254 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/269254
Semiconductor device having trench gate electrodes formed in first pillars including source layers formed in the first pillars being deeper into the substrate than first source layers in second pillars Oct 24, 2018 Issued
Array ( [id] => 16301247 [patent_doc_number] => 20200286970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => OLED DISPLAY PANEL AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/475871 [patent_app_country] => US [patent_app_date] => 2018-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3837 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16475871 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/475871
OLED DISPLAY PANEL AND MANUFACTURING METHOD THEREOF Oct 9, 2018 Abandoned
Array ( [id] => 15718323 [patent_doc_number] => 20200105929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => GATE-ALL-AROUND FIELD-EFFECT TRANSISTOR WITH ASYMMETRIC THRESHOLD VOLTAGE [patent_app_type] => utility [patent_app_number] => 16/147680 [patent_app_country] => US [patent_app_date] => 2018-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7233 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147680 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147680
Fabricating a gate-all-around (GAA) field effect transistor having threshold voltage asymmetry by thinning source side lateral end portion of the nanosheet layer Sep 28, 2018 Issued
Array ( [id] => 14191611 [patent_doc_number] => 20190115511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => Light Emitting Diode and Fabrication Method Thereof [patent_app_type] => utility [patent_app_number] => 16/147604 [patent_app_country] => US [patent_app_date] => 2018-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147604 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147604
Light Emitting Diode and Fabrication Method Thereof Sep 28, 2018 Abandoned
Array ( [id] => 15718379 [patent_doc_number] => 20200105957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => PHOTODIODE HAVING LIGHT REDIRECTION LAYER [patent_app_type] => utility [patent_app_number] => 16/147507 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147507 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147507
PHOTODIODE HAVING LIGHT REDIRECTION LAYER Sep 27, 2018 Abandoned
Array ( [id] => 14110537 [patent_doc_number] => 20190096944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => SOLID-STATE IMAGE PICKUP DEVICE AND MANUFACTURING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 16/147382 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147382 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147382
SOLID-STATE IMAGE PICKUP DEVICE AND MANUFACTURING METHOD OF THE SAME Sep 27, 2018 Abandoned
Array ( [id] => 13878213 [patent_doc_number] => 20190035447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => Magnetic tunnel junction with TMR enhancement [patent_app_type] => utility [patent_app_number] => 16/147463 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147463 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147463
Magnetic tunnel junction with TMR enhancement Sep 27, 2018 Abandoned
Array ( [id] => 13832999 [patent_doc_number] => 20190019984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => ORGANIC LIGHT-EMITTING DIODE DISPLAY AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/121521 [patent_app_country] => US [patent_app_date] => 2018-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7580 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16121521 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/121521
Method of manufacturing an organic light-emitting diode (OLED) display having sealing member comprising through-portions formed in first and second metal layers Sep 3, 2018 Issued
Array ( [id] => 18464478 [patent_doc_number] => 11688775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Method of forming first and second contacts self-aligned top source/drain region of a vertical field-effect transistor [patent_app_type] => utility [patent_app_number] => 16/101981 [patent_app_country] => US [patent_app_date] => 2018-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 7976 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16101981 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/101981
Method of forming first and second contacts self-aligned top source/drain region of a vertical field-effect transistor Aug 12, 2018 Issued
Array ( [id] => 15503757 [patent_doc_number] => 20200052067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR PREPARING THE SAME [patent_app_type] => utility [patent_app_number] => 16/102125 [patent_app_country] => US [patent_app_date] => 2018-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6879 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16102125 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/102125
SEMICONDUCTOR STRUCTURE AND METHOD FOR PREPARING THE SAME Aug 12, 2018 Abandoned
Array ( [id] => 15503811 [patent_doc_number] => 20200052094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => BOTTOM SPACER STRUCTURE FOR VERTICAL FIELD EFFECT TRANSISTOR AND METHOD OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 16/102110 [patent_app_country] => US [patent_app_date] => 2018-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16102110 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/102110
Space deposition between source/drain and sacrificial layers Aug 12, 2018 Issued
Array ( [id] => 14317689 [patent_doc_number] => 20190148548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => Dual Gate Dielectric Transistor [patent_app_type] => utility [patent_app_number] => 16/102126 [patent_app_country] => US [patent_app_date] => 2018-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16102126 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/102126
Dual Gate Dielectric Transistor Aug 12, 2018 Pending
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