Search

Willis Little

Examiner (ID: 2267)

Most Active Art Unit
3203
Art Unit(s)
2103, 2401, 3203, 2403, 2107, 2406, 2899, 3616, 3643
Total Applications
2327
Issued Applications
2182
Pending Applications
48
Abandoned Applications
97

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15503247 [patent_doc_number] => 20200051812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => PREVENTING DELAMINATION AT SILICON/DIELECTIC INTERFACE [patent_app_type] => utility [patent_app_number] => 16/056811 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056811 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/056811
PREVENTING DELAMINATION AT SILICON/DIELECTIC INTERFACE Aug 6, 2018 Abandoned
Array ( [id] => 15504015 [patent_doc_number] => 20200052196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => Avoiding Oxygen Plasma Damage During Hard Mask Etching in Magnetic Tunnel Junction (MTJ) Fabrication Process [patent_app_type] => utility [patent_app_number] => 16/056770 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056770 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/056770
Avoiding Oxygen Plasma Damage During Hard Mask Etching in Magnetic Tunnel Junction (MTJ) Fabrication Process Aug 6, 2018 Abandoned
Array ( [id] => 17094491 [patent_doc_number] => 11122697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Method of fabricating an electronic medical device, including overmolding an assembly with thermoplastic material [patent_app_type] => utility [patent_app_number] => 16/057656 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3289 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057656 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057656
Method of fabricating an electronic medical device, including overmolding an assembly with thermoplastic material Aug 6, 2018 Issued
Array ( [id] => 13935945 [patent_doc_number] => 20190051488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => Ion Implantation Apparatus and Method of Manufacturing Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 16/057014 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10474 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057014 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057014
Ion Implantation Apparatus and Method of Manufacturing Semiconductor Devices Aug 6, 2018 Abandoned
Array ( [id] => 17395988 [patent_doc_number] => 11245013 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Silicon carbide semiconductor device having a step film formed between a plating film and a first electrode [patent_app_type] => utility [patent_app_number] => 16/050401 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 8120 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16050401 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/050401
Silicon carbide semiconductor device having a step film formed between a plating film and a first electrode Jul 30, 2018 Issued
Array ( [id] => 13909555 [patent_doc_number] => 20190043982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => Transistor Device with Trench Edge Termination [patent_app_type] => utility [patent_app_number] => 16/050950 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16050950 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/050950
Transistor Device with Trench Edge Termination Jul 30, 2018 Abandoned
Array ( [id] => 14446563 [patent_doc_number] => 20190181155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 16/049958 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16049958 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/049958
DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL Jul 30, 2018 Abandoned
Array ( [id] => 13936143 [patent_doc_number] => 20190051587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => IC PACKAGE [patent_app_type] => utility [patent_app_number] => 16/050113 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7032 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16050113 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/050113
IC PACKAGE Jul 30, 2018 Abandoned
Array ( [id] => 15461921 [patent_doc_number] => 20200043785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => A CONTACT STRUCTURE HAVING A FIRST LINER AND A SECOND LINER FORMED BETWEEN A CONDUCTIVE ELEMENT AND A INSULATING LAYER [patent_app_type] => utility [patent_app_number] => 16/050233 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16050233 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/050233
A CONTACT STRUCTURE HAVING A FIRST LINER AND A SECOND LINER FORMED BETWEEN A CONDUCTIVE ELEMENT AND A INSULATING LAYER Jul 30, 2018 Abandoned
Array ( [id] => 13879353 [patent_doc_number] => 20190036017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => MAGNETIC SWITCHING MATERIALS AND PREPARATION THEREOF [patent_app_type] => utility [patent_app_number] => 16/050091 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16050091 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/050091
MAGNETIC SWITCHING MATERIALS AND PREPARATION THEREOF Jul 30, 2018 Abandoned
Array ( [id] => 13598573 [patent_doc_number] => 20180350835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => Semiconductor Devices Including a Thin Film [patent_app_type] => utility [patent_app_number] => 16/049510 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16049510 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/049510
Semiconductor Devices Including a Thin Film Jul 29, 2018 Abandoned
Array ( [id] => 13543177 [patent_doc_number] => 20180323135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => Method And System For Improved Matching For On-Chip Capacitors [patent_app_type] => utility [patent_app_number] => 16/030397 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030397 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030397
Method And System For Improved Matching For On-Chip Capacitors Jul 8, 2018 Abandoned
Array ( [id] => 16415813 [patent_doc_number] => 10823696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Method of fabricating a biological field-effect transistor (BioFET) with increased sensing area [patent_app_type] => utility [patent_app_number] => 16/021077 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6460 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16021077 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/021077
Method of fabricating a biological field-effect transistor (BioFET) with increased sensing area Jun 27, 2018 Issued
Array ( [id] => 15015791 [patent_doc_number] => 10454060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Method of manufacturing an organic light emitting display device having a hollow space formed between a portion of first and third contact electrodes under a protective electrode [patent_app_type] => utility [patent_app_number] => 16/013840 [patent_app_country] => US [patent_app_date] => 2018-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 10357 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16013840 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/013840
Method of manufacturing an organic light emitting display device having a hollow space formed between a portion of first and third contact electrodes under a protective electrode Jun 19, 2018 Issued
Array ( [id] => 14875605 [patent_doc_number] => 20190288044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => ELECTROLUMINESCENT DIODE ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 16/308883 [patent_app_country] => US [patent_app_date] => 2018-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16308883 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/308883
ELECTROLUMINESCENT DIODE ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY PANEL Jun 19, 2018 Abandoned
Array ( [id] => 13630123 [patent_doc_number] => 20180366614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => MANGANESE-DOPED RED FLUORIDE PHOSPHOR, LIGHT EMITTING DEVICE, AND BACKLIGHT MODULE [patent_app_type] => utility [patent_app_number] => 15/993616 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15993616 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/993616
MANGANESE-DOPED RED FLUORIDE PHOSPHOR, LIGHT EMITTING DEVICE, AND BACKLIGHT MODULE May 30, 2018 Abandoned
Array ( [id] => 13613827 [patent_doc_number] => 20180358463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/993708 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15993708 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/993708
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE May 30, 2018 Abandoned
Array ( [id] => 19444647 [patent_doc_number] => 12094939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Semiconductor device having a gate electrode, an interlayer insulating film and a barrier metal provided in a trench [patent_app_type] => utility [patent_app_number] => 15/993671 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 6986 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15993671 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/993671
Semiconductor device having a gate electrode, an interlayer insulating film and a barrier metal provided in a trench May 30, 2018 Issued
Array ( [id] => 17938768 [patent_doc_number] => 11473212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Group 13 (III) nitride thick layer formed on an underlying layer having high and low carrier concentration regions with different defect densities [patent_app_type] => utility [patent_app_number] => 15/991317 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 6750 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991317 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/991317
Group 13 (III) nitride thick layer formed on an underlying layer having high and low carrier concentration regions with different defect densities May 28, 2018 Issued
Array ( [id] => 17938768 [patent_doc_number] => 11473212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Group 13 (III) nitride thick layer formed on an underlying layer having high and low carrier concentration regions with different defect densities [patent_app_type] => utility [patent_app_number] => 15/991317 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 6750 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991317 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/991317
Group 13 (III) nitride thick layer formed on an underlying layer having high and low carrier concentration regions with different defect densities May 28, 2018 Issued
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