Willis Little

Array ( [id] => 16781696 [patent_doc_number] => 20210118775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/655178 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4284 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17181329 [patent_doc_number] => 11158578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => High density interconnect device and method [patent_app_type] => utility [patent_app_number] => 16/601297 [patent_app_country] => US [patent_app_date] => 2019-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2644 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16601297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16835301 [patent_doc_number] => 11011561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Pixel and image sensor including the same [patent_app_type] => utility [patent_app_number] => 16/598917 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16598917 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16911516 [patent_doc_number] => 11043566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Semiconductor structures in a wide gate pitch region of semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/599116 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 7034 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599116 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16394532 [patent_doc_number] => 20200335473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => Semiconductor Wafer, Bonding Structure And Wafer Bonding Method [patent_app_type] => utility [patent_app_number] => 16/598898 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16598898 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15443295 [patent_doc_number] => 20200035831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => MOS DEVICES HAVING EPITAXY REGIONS WITH REDUCED FACETS [patent_app_type] => utility [patent_app_number] => 16/592050 [patent_app_country] => US [patent_app_date] => 2019-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4329 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16592050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15462175 [patent_doc_number] => 20200043912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => SERIES RESISTOR OVER DRAIN REGION IN HIGH VOLTAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/584795 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3786 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16584795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16645599 [patent_doc_number] => 10923467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Series resistor over drain region in high voltage device [patent_app_type] => utility [patent_app_number] => 16/584773 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 3785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16584773 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16448281 [patent_doc_number] => 10840212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Bonding package components through plating [patent_app_type] => utility [patent_app_number] => 16/580666 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16580666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16715885 [patent_doc_number] => 20210083032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => ARRAY SUBSTRATE AND OLED DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/616462 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16616462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16433113 [patent_doc_number] => 10833213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Optical cladding layer design [patent_app_type] => utility [patent_app_number] => 16/548260 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3537 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16548260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15185043 [patent_doc_number] => 20190363113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => OPTICAL SENSOR HAVING TWO TAPS FOR PHOTON-GENERATED ELECTRONS OF VISIBLE AND IR LIGHT [patent_app_type] => utility [patent_app_number] => 16/532570 [patent_app_country] => US [patent_app_date] => 2019-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16532570 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15093015 [patent_doc_number] => 20190341319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => Packaging Mechanisms for Dies with Different Sizes of Connectors [patent_app_type] => utility [patent_app_number] => 16/512060 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16512060 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16850891 [patent_doc_number] => 20210151636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => ELECTRONIC COMPONENT-MOUNTED PACKAGE AND ELECTRONIC MODULE [patent_app_type] => utility [patent_app_number] => 17/256038 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17256038 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15791801 [patent_doc_number] => 10629633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Array substrate and manufacturing method thereof, display device [patent_app_type] => utility [patent_app_number] => 16/456352 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3795 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16456352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15331625 [patent_doc_number] => 20200006142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => METHOD FOR PRODUCING A THROUGH SEMICONDUCTOR VIA CONNECTION [patent_app_type] => utility [patent_app_number] => 16/456833 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16456833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14969317 [patent_doc_number] => 20190312137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => HIGH-ELECTRON-MOBILITY TRANSISTOR WITH BURIED INTERCONNECT [patent_app_type] => utility [patent_app_number] => 16/450513 [patent_app_country] => US [patent_app_date] => 2019-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16450513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18263147 [patent_doc_number] => 11610856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Connectivity between integrated circuit dice in a multi-chip package [patent_app_type] => utility [patent_app_number] => 16/449923 [patent_app_country] => US [patent_app_date] => 2019-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 6362 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16449923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15139537 [patent_doc_number] => 10483255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/448241 [patent_app_country] => US [patent_app_date] => 2019-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 9059 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16448241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14938669 [patent_doc_number] => 20190304973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => SEMICONDCUTOR DEVICE INCLUDING A SEMICONDUCTOR EXTENSION LAYER BETWEEN ACTIVE REGIONS [patent_app_type] => utility [patent_app_number] => 16/444683 [patent_app_country] => US [patent_app_date] => 2019-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16444683 [rel_patent_id] =>[rel_patent_doc_number] =>)