Search

Willis Little

Examiner (ID: 13674)

Most Active Art Unit
3203
Art Unit(s)
2899, 3643, 2107, 2403, 2406, 3203, 3616, 2401, 2103
Total Applications
2327
Issued Applications
2182
Pending Applications
48
Abandoned Applications
97

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15109159 [patent_doc_number] => 10475911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Semiconductor device having a source region with chalcogen atoms [patent_app_type] => utility [patent_app_number] => 16/254235 [patent_app_country] => US [patent_app_date] => 2019-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16254235 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/254235
Semiconductor device having a source region with chalcogen atoms Jan 21, 2019 Issued
Array ( [id] => 16180447 [patent_doc_number] => 20200227416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => 3D 1T1C STACKED DRAM STRUCTURE AND METHOD TO FABRICATE [patent_app_type] => utility [patent_app_number] => 16/247321 [patent_app_country] => US [patent_app_date] => 2019-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16247321 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/247321
3D 1T1C stacked DRAM structure and method to fabricate Jan 13, 2019 Issued
Array ( [id] => 14285411 [patent_doc_number] => 20190139990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => DISPLAY DEVICE WITH DIFFERENT CIRCUIT GROUPS [patent_app_type] => utility [patent_app_number] => 16/237864 [patent_app_country] => US [patent_app_date] => 2019-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237864 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/237864
Display device with different circuit groups Jan 1, 2019 Issued
Array ( [id] => 14285111 [patent_doc_number] => 20190139840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => WAFER SCALE TESTING AND INITIALIZATION OF SMALL DIE CHIPS [patent_app_type] => utility [patent_app_number] => 16/234852 [patent_app_country] => US [patent_app_date] => 2018-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4002 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16234852 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/234852
WAFER SCALE TESTING AND INITIALIZATION OF SMALL DIE CHIPS Dec 27, 2018 Abandoned
Array ( [id] => 14588321 [patent_doc_number] => 20190221769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => OLED SUBSTRATE AND PACKAGING METHOD AND DISPLAY APPARATUS THEREOF [patent_app_type] => utility [patent_app_number] => 16/228909 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228909 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228909
OLED substrate and packaging method and display apparatus thereof Dec 20, 2018 Issued
Array ( [id] => 17326491 [patent_doc_number] => 11217516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same [patent_app_type] => utility [patent_app_number] => 16/231238 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 5978 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16231238 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/231238
Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same Dec 20, 2018 Issued
Array ( [id] => 14317191 [patent_doc_number] => 20190148299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => CONTACT FORMATION IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/226911 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226911 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226911
Contact formation in semiconductor devices Dec 19, 2018 Issued
Array ( [id] => 15611495 [patent_doc_number] => 10586818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Solid-state imaging device, camera module and electronic apparatus [patent_app_type] => utility [patent_app_number] => 16/213176 [patent_app_country] => US [patent_app_date] => 2018-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 35094 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16213176 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/213176
Solid-state imaging device, camera module and electronic apparatus Dec 6, 2018 Issued
Array ( [id] => 16928479 [patent_doc_number] => 11049971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Semiconductor device having epitaxial structure [patent_app_type] => utility [patent_app_number] => 16/205233 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5145 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16205233 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/205233
Semiconductor device having epitaxial structure Nov 29, 2018 Issued
Array ( [id] => 14110637 [patent_doc_number] => 20190096994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => Electronic Systems and Methods of Forming Semiconductor Constructions [patent_app_type] => utility [patent_app_number] => 16/200593 [patent_app_country] => US [patent_app_date] => 2018-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16200593 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/200593
Electronic systems and methods of forming semiconductor constructions Nov 25, 2018 Issued
Array ( [id] => 15791591 [patent_doc_number] => 10629527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Method of manufacturing semiconductor device with multi wire structure [patent_app_type] => utility [patent_app_number] => 16/196366 [patent_app_country] => US [patent_app_date] => 2018-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3931 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16196366 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/196366
Method of manufacturing semiconductor device with multi wire structure Nov 19, 2018 Issued
Array ( [id] => 15807893 [patent_doc_number] => 20200127089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/194379 [patent_app_country] => US [patent_app_date] => 2018-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16194379 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/194379
Semiconductor device including conductive structure and manufacturing method thereof Nov 17, 2018 Issued
Array ( [id] => 16264474 [patent_doc_number] => 10755918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Spacer with laminate liner [patent_app_type] => utility [patent_app_number] => 16/193313 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1971 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16193313 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/193313
Spacer with laminate liner Nov 15, 2018 Issued
Array ( [id] => 15286711 [patent_doc_number] => 10516026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Split gate memory device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 16/166603 [patent_app_country] => US [patent_app_date] => 2018-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 4263 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16166603 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/166603
Split gate memory device and method of fabricating the same Oct 21, 2018 Issued
Array ( [id] => 15260283 [patent_doc_number] => 20190378875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => DISPLAY SUBSTRATE, DISPLAY PANEL, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/472341 [patent_app_country] => US [patent_app_date] => 2018-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16472341 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/472341
Display substrate, display panel, and display device having electrostriction layer Oct 15, 2018 Issued
Array ( [id] => 13936327 [patent_doc_number] => 20190051679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => Array Substrate and Display Device [patent_app_type] => utility [patent_app_number] => 16/160223 [patent_app_country] => US [patent_app_date] => 2018-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4303 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16160223 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/160223
Array substrate and display device Oct 14, 2018 Issued
Array ( [id] => 13936239 [patent_doc_number] => 20190051635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => CHIP PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/159816 [patent_app_country] => US [patent_app_date] => 2018-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16159816 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/159816
Chip package structure with conductive shielding film Oct 14, 2018 Issued
Array ( [id] => 13936173 [patent_doc_number] => 20190051602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => THROUGH-HOLES OF A SEMICONDUCTOR CHIP [patent_app_type] => utility [patent_app_number] => 16/157933 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157933 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/157933
Through-holes of a semiconductor chip Oct 10, 2018 Issued
Array ( [id] => 15688525 [patent_doc_number] => 20200098926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => TRANSISTORS WITH FERROELECTRIC GATES [patent_app_type] => utility [patent_app_number] => 16/142940 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16142940 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/142940
TRANSISTORS WITH FERROELECTRIC GATES Sep 25, 2018 Abandoned
Array ( [id] => 14366829 [patent_doc_number] => 10304726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/137972 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 55 [patent_no_of_words] => 19258 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137972 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/137972
Semiconductor device and manufacturing method thereof Sep 20, 2018 Issued
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