Search

Willis Little

Examiner (ID: 2267)

Most Active Art Unit
3203
Art Unit(s)
2103, 2401, 3203, 2403, 2107, 2406, 2899, 3616, 3643
Total Applications
2327
Issued Applications
2182
Pending Applications
48
Abandoned Applications
97

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8154833 [patent_doc_number] => 20120098092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'SEMICONDUCTOR DEVICE CAPACITORS INCLUDING MULTILAYERED LOWER ELECTRODES' [patent_app_type] => utility [patent_app_number] => 13/271821 [patent_app_country] => US [patent_app_date] => 2011-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 6688 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20120098092.pdf [firstpage_image] =>[orig_patent_app_number] => 13271821 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/271821
SEMICONDUCTOR DEVICE CAPACITORS INCLUDING MULTILAYERED LOWER ELECTRODES Oct 11, 2011 Abandoned
Array ( [id] => 10838536 [patent_doc_number] => 08866214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Vertical transistor having an asymmetric gate' [patent_app_type] => utility [patent_app_number] => 13/271812 [patent_app_country] => US [patent_app_date] => 2011-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 3700 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 500 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13271812 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/271812
Vertical transistor having an asymmetric gate Oct 11, 2011 Issued
Array ( [id] => 8765060 [patent_doc_number] => 20130093097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'Package-On-Package (PoP) Structure and Method' [patent_app_type] => utility [patent_app_number] => 13/271952 [patent_app_country] => US [patent_app_date] => 2011-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 5662 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13271952 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/271952
Package-on-package (PoP) structure having at least one package comprising one die being disposed in a core material between first and second surfaces of the core material Oct 11, 2011 Issued
Array ( [id] => 9273996 [patent_doc_number] => 08637929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-28 [patent_title] => 'LDMOS transistor having a gate electrode formed over thick and thin portions of a gate insulation film' [patent_app_type] => utility [patent_app_number] => 13/270661 [patent_app_country] => US [patent_app_date] => 2011-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 62 [patent_no_of_words] => 12115 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13270661 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/270661
LDMOS transistor having a gate electrode formed over thick and thin portions of a gate insulation film Oct 10, 2011 Issued
Array ( [id] => 11300875 [patent_doc_number] => 09508886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Method for making a crystalline silicon solar cell substrate utilizing flat top laser beam' [patent_app_type] => utility [patent_app_number] => 13/271212 [patent_app_country] => US [patent_app_date] => 2011-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 67 [patent_no_of_words] => 9356 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13271212 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/271212
Method for making a crystalline silicon solar cell substrate utilizing flat top laser beam Oct 10, 2011 Issued
Array ( [id] => 8122889 [patent_doc_number] => 20120085990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-12 [patent_title] => 'SUPERLATTICE QUANTUM WELL INFRARED DETECTOR HAVING EXPOSED LAYERS' [patent_app_type] => utility [patent_app_number] => 13/270727 [patent_app_country] => US [patent_app_date] => 2011-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5776 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20120085990.pdf [firstpage_image] =>[orig_patent_app_number] => 13270727 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/270727
SUPERLATTICE QUANTUM WELL INFRARED DETECTOR HAVING EXPOSED LAYERS Oct 10, 2011 Abandoned
Array ( [id] => 9144462 [patent_doc_number] => 20130298985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'MICROELECTRONIC STRUCTURES INCLUDING CUPROUS OXIDE SEMICONDUCTORS AND HAVING IMPROVED P-N HETEROJUNCTIONS' [patent_app_type] => utility [patent_app_number] => 13/876652 [patent_app_country] => US [patent_app_date] => 2011-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9844 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13876652 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/876652
MICROELECTRONIC STRUCTURES INCLUDING CUPROUS OXIDE SEMICONDUCTORS AND HAVING IMPROVED P-N HETEROJUNCTIONS Sep 28, 2011 Abandoned
Array ( [id] => 8664928 [patent_doc_number] => 08378390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Silicon carbide bipolar junction transistor (BJT) having a surface electrode disposed on top of a dielectric layer formed at a region between emitter contact and base contact' [patent_app_type] => utility [patent_app_number] => 13/243056 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3618 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13243056 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/243056
Silicon carbide bipolar junction transistor (BJT) having a surface electrode disposed on top of a dielectric layer formed at a region between emitter contact and base contact Sep 22, 2011 Issued
Array ( [id] => 7728080 [patent_doc_number] => 20120012839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'OXIDE THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/243584 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5198 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20120012839.pdf [firstpage_image] =>[orig_patent_app_number] => 13243584 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/243584
Oxide thin film transistor having source and drain electrodes being formed between a primary and a secondary active layers Sep 22, 2011 Issued
Array ( [id] => 7743495 [patent_doc_number] => 20120021581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'SELF-ALIGNED CONTACT STRUCTURE LATERALLY ENCLOSED BY AN ISOLATION STRUCTURE OF A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/237268 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9386 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20120021581.pdf [firstpage_image] =>[orig_patent_app_number] => 13237268 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/237268
SELF-ALIGNED CONTACT STRUCTURE LATERALLY ENCLOSED BY AN ISOLATION STRUCTURE OF A SEMICONDUCTOR DEVICE Sep 19, 2011 Abandoned
Array ( [id] => 7666892 [patent_doc_number] => 20110316161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'METHOD OF PRODUCING A DUAL DAMASCENE MULTILAYER INTERCONNECTION AND MULTILAYER INTERCONNECTION STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/227031 [patent_app_country] => US [patent_app_date] => 2011-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8712 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13227031 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/227031
METHOD OF PRODUCING A DUAL DAMASCENE MULTILAYER INTERCONNECTION AND MULTILAYER INTERCONNECTION STRUCTURE Sep 6, 2011 Abandoned
Array ( [id] => 8505889 [patent_doc_number] => 20120305298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'BUMP WITH NANOLAMINATED STRUCTURE, PACKAGE STRUCTURE OF THE SAME, AND METHOD OF PREPARING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/219707 [patent_app_country] => US [patent_app_date] => 2011-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6386 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13219707 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/219707
BUMP WITH NANOLAMINATED STRUCTURE, PACKAGE STRUCTURE OF THE SAME, AND METHOD OF PREPARING THE SAME Aug 27, 2011 Abandoned
Array ( [id] => 7564822 [patent_doc_number] => 20110284885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'LIGHT EMITTIG DEVICE PACKAGE AND IMAGE DISPLAY APPARATUS INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/197285 [patent_app_country] => US [patent_app_date] => 2011-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20110284885.pdf [firstpage_image] =>[orig_patent_app_number] => 13197285 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/197285
LIGHT EMITTIG DEVICE PACKAGE AND IMAGE DISPLAY APPARATUS INCLUDING THE SAME Aug 2, 2011 Abandoned
Array ( [id] => 7699609 [patent_doc_number] => 20110226981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'MULTILAYERED CAP BARRIER IN MICROELECTRONIC INTERCONNECT STRUCTURES' [patent_app_type] => utility [patent_app_number] => 13/117536 [patent_app_country] => US [patent_app_date] => 2011-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5014 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20110226981.pdf [firstpage_image] =>[orig_patent_app_number] => 13117536 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/117536
MULTILAYERED CAP BARRIER IN MICROELECTRONIC INTERCONNECT STRUCTURES May 26, 2011 Abandoned
Array ( [id] => 6015878 [patent_doc_number] => 20110223724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'Semiconductor device having low parasitic resistance and small junction leakage characteristic and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/067214 [patent_app_country] => US [patent_app_date] => 2011-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4876 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20110223724.pdf [firstpage_image] =>[orig_patent_app_number] => 13067214 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/067214
Semiconductor device having low parasitic resistance and small junction leakage characteristic and method of manufacturing the same May 16, 2011 Abandoned
Array ( [id] => 6042434 [patent_doc_number] => 20110204511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-25 [patent_title] => 'System and Method for Improving Reliability of Integrated Circuit Packages' [patent_app_type] => utility [patent_app_number] => 13/099055 [patent_app_country] => US [patent_app_date] => 2011-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4703 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20110204511.pdf [firstpage_image] =>[orig_patent_app_number] => 13099055 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/099055
System and Method for Improving Reliability of Integrated Circuit Packages May 1, 2011 Abandoned
Array ( [id] => 11300612 [patent_doc_number] => 09508622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Method for protecting copper wire bonds on aluminum pads of a semiconductor device from corrosion' [patent_app_type] => utility [patent_app_number] => 13/096102 [patent_app_country] => US [patent_app_date] => 2011-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13096102 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/096102
Method for protecting copper wire bonds on aluminum pads of a semiconductor device from corrosion Apr 27, 2011 Issued
Array ( [id] => 8403189 [patent_doc_number] => 20120235244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'Semiconductor Structure and Method for Manufacturing the Same' [patent_app_type] => utility [patent_app_number] => 13/380482 [patent_app_country] => US [patent_app_date] => 2011-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8924 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13380482 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/380482
Semiconductor Structure and Method for Manufacturing the Same Apr 17, 2011 Abandoned
Array ( [id] => 8603944 [patent_doc_number] => 20130009256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/635312 [patent_app_country] => US [patent_app_date] => 2011-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 15890 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13635312 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/635312
SEMICONDUCTOR DEVICE Mar 29, 2011 Abandoned
Array ( [id] => 8180077 [patent_doc_number] => 20120112252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/380380 [patent_app_country] => US [patent_app_date] => 2011-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5460 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20120112252.pdf [firstpage_image] =>[orig_patent_app_number] => 13380380 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/380380
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME Feb 26, 2011 Abandoned
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