Search

Willis Little

Examiner (ID: 2267)

Most Active Art Unit
3203
Art Unit(s)
2103, 2401, 3203, 2403, 2107, 2406, 2899, 3616, 3643
Total Applications
2327
Issued Applications
2182
Pending Applications
48
Abandoned Applications
97

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8154621 [patent_doc_number] => 20120097985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'Light Emitting Diode (LED) Package And Method Of Fabrication' [patent_app_type] => utility [patent_app_number] => 12/909367 [patent_app_country] => US [patent_app_date] => 2010-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3509 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20120097985.pdf [firstpage_image] =>[orig_patent_app_number] => 12909367 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/909367
Light Emitting Diode (LED) Package And Method Of Fabrication Oct 20, 2010 Abandoned
Array ( [id] => 7506811 [patent_doc_number] => 20110254148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-20 [patent_title] => 'SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/908500 [patent_app_country] => US [patent_app_date] => 2010-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20110254148.pdf [firstpage_image] =>[orig_patent_app_number] => 12908500 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/908500
Semicondutor device package placed within fitting portion of wiring member and attached to heat sink Oct 19, 2010 Issued
Array ( [id] => 8154710 [patent_doc_number] => 20120098035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'Group III-N HEMT with an Increased Buffer Breakdown Voltage' [patent_app_type] => utility [patent_app_number] => 12/908458 [patent_app_country] => US [patent_app_date] => 2010-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4134 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20120098035.pdf [firstpage_image] =>[orig_patent_app_number] => 12908458 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/908458
Group III-nitride HEMT having a well region formed on the surface of substrate and contacted the buffer layer to increase breakdown voltage and the method for forming the same Oct 19, 2010 Issued
Array ( [id] => 8982584 [patent_doc_number] => 08513703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Group III-nitride HEMT with multi-layered substrate having a second layer of one conductivity type touching a top surface of a first layers of different conductivity type and a method for forming the same' [patent_app_type] => utility [patent_app_number] => 12/908514 [patent_app_country] => US [patent_app_date] => 2010-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 6061 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 398 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12908514 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/908514
Group III-nitride HEMT with multi-layered substrate having a second layer of one conductivity type touching a top surface of a first layers of different conductivity type and a method for forming the same Oct 19, 2010 Issued
Array ( [id] => 6036294 [patent_doc_number] => 20110089417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/906565 [patent_app_country] => US [patent_app_date] => 2010-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15361 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20110089417.pdf [firstpage_image] =>[orig_patent_app_number] => 12906565 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/906565
SEMICONDUCTOR DEVICE Oct 17, 2010 Abandoned
Array ( [id] => 9286083 [patent_doc_number] => 08642412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-04 [patent_title] => 'Method for manufacturing an oxide-based semiconductor thin film transistor (TFT) including out diffusing hydrogen or moisture from the oxide semiconductor layer into an adjacent insulating layer which contains a halogen element' [patent_app_type] => utility [patent_app_number] => 12/906175 [patent_app_country] => US [patent_app_date] => 2010-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 63 [patent_no_of_words] => 44327 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12906175 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/906175
Method for manufacturing an oxide-based semiconductor thin film transistor (TFT) including out diffusing hydrogen or moisture from the oxide semiconductor layer into an adjacent insulating layer which contains a halogen element Oct 17, 2010 Issued
Array ( [id] => 7815205 [patent_doc_number] => 20120061825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'CHIP SCALE PACKAGE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/906501 [patent_app_country] => US [patent_app_date] => 2010-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5010 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20120061825.pdf [firstpage_image] =>[orig_patent_app_number] => 12906501 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/906501
CHIP SCALE PACKAGE AND METHOD OF FABRICATING THE SAME Oct 17, 2010 Abandoned
Array ( [id] => 6036509 [patent_doc_number] => 20110089558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/906122 [patent_app_country] => US [patent_app_date] => 2010-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 22893 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20110089558.pdf [firstpage_image] =>[orig_patent_app_number] => 12906122 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/906122
SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF Oct 16, 2010 Abandoned
Array ( [id] => 6177647 [patent_doc_number] => 20110121380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'NON-VOLATILE ELECTRICALLY ALTERABLE MEMORY CELL FOR STORING MULTIPLE DATA' [patent_app_type] => utility [patent_app_number] => 12/902614 [patent_app_country] => US [patent_app_date] => 2010-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6509 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20110121380.pdf [firstpage_image] =>[orig_patent_app_number] => 12902614 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/902614
NON-VOLATILE ELECTRICALLY ALTERABLE MEMORY CELL FOR STORING MULTIPLE DATA Oct 11, 2010 Abandoned
Array ( [id] => 8245282 [patent_doc_number] => 08203210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-19 [patent_title] => 'Semiconductor device having metal contacts formed in an interlayer dielectric film comprising four silicon-containing layers' [patent_app_type] => utility [patent_app_number] => 12/883031 [patent_app_country] => US [patent_app_date] => 2010-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 20765 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/203/08203210.pdf [firstpage_image] =>[orig_patent_app_number] => 12883031 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/883031
Semiconductor device having metal contacts formed in an interlayer dielectric film comprising four silicon-containing layers Sep 14, 2010 Issued
Array ( [id] => 6004055 [patent_doc_number] => 20110057258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => 'DUAL STRESS DEVICE AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/875416 [patent_app_country] => US [patent_app_date] => 2010-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20110057258.pdf [firstpage_image] =>[orig_patent_app_number] => 12875416 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/875416
Semiconductor structure having a gate electrode at least partially disposed in a trench formed at a bend in a semiconductor material Sep 2, 2010 Issued
Array ( [id] => 6609744 [patent_doc_number] => 20100323477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'INTERCONNECTIONS OF AN INTEGRATED ELECTRONIC CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/854077 [patent_app_country] => US [patent_app_date] => 2010-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4787 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0323/20100323477.pdf [firstpage_image] =>[orig_patent_app_number] => 12854077 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/854077
INTERCONNECTIONS OF AN INTEGRATED ELECTRONIC CIRCUIT Aug 9, 2010 Abandoned
Array ( [id] => 6557133 [patent_doc_number] => 20100289117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-18 [patent_title] => 'SHALLOW TRENCH ISOLATION STRUCTURE INCLUDING SECOND LINER COVERING CORNER OF TRENCH AND FIRST LINER' [patent_app_type] => utility [patent_app_number] => 12/844088 [patent_app_country] => US [patent_app_date] => 2010-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2154 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20100289117.pdf [firstpage_image] =>[orig_patent_app_number] => 12844088 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/844088
SHALLOW TRENCH ISOLATION STRUCTURE INCLUDING SECOND LINER COVERING CORNER OF TRENCH AND FIRST LINER Jul 26, 2010 Abandoned
Array ( [id] => 6570057 [patent_doc_number] => 20100273309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'METHOD FOR FORMING A SELF ALIGNED ISOLATION TRENCH' [patent_app_type] => utility [patent_app_number] => 12/828868 [patent_app_country] => US [patent_app_date] => 2010-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6000 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20100273309.pdf [firstpage_image] =>[orig_patent_app_number] => 12828868 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/828868
Method for forming a self-aligned isolation structure utilizing sidewall spacers as an etch mask and remaining as a portion of the isolation structure Jun 30, 2010 Issued
Array ( [id] => 8154514 [patent_doc_number] => 20120097922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'LIGHT EMITTING ELEMENT, METHOD OF PRODUCING SAME, LAMP, ELECTRONIC EQUIPMENT, AND MECHINICAL APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/380429 [patent_app_country] => US [patent_app_date] => 2010-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 16187 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20120097922.pdf [firstpage_image] =>[orig_patent_app_number] => 13380429 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/380429
LIGHT EMITTING ELEMENT, METHOD OF PRODUCING SAME, LAMP, ELECTRONIC EQUIPMENT, AND MECHINICAL APPARATUS Jun 17, 2010 Abandoned
Array ( [id] => 6161406 [patent_doc_number] => 20110193221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => '3DIC Architecture with Interposer for Bonding Dies' [patent_app_type] => utility [patent_app_number] => 12/774558 [patent_app_country] => US [patent_app_date] => 2010-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 3584 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20110193221.pdf [firstpage_image] =>[orig_patent_app_number] => 12774558 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774558
3D IC architecture with interposer and interconnect structure for bonding dies May 4, 2010 Issued
Array ( [id] => 6026995 [patent_doc_number] => 20110079872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-07 [patent_title] => 'PASSIVE DEVICE, SEMICONDUCTOR MODULE, ELECTRONIC CIRCUIT BOARD, AND ELECTRONIC SYSTEM HAVING THE PASSIVE DEVICE, AND METHODS OF FABRICATING AND INSPECTING THE SEMICONDUCTOR MODULE' [patent_app_type] => utility [patent_app_number] => 12/772351 [patent_app_country] => US [patent_app_date] => 2010-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5733 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20110079872.pdf [firstpage_image] =>[orig_patent_app_number] => 12772351 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/772351
PASSIVE DEVICE, SEMICONDUCTOR MODULE, ELECTRONIC CIRCUIT BOARD, AND ELECTRONIC SYSTEM HAVING THE PASSIVE DEVICE, AND METHODS OF FABRICATING AND INSPECTING THE SEMICONDUCTOR MODULE May 2, 2010 Abandoned
Array ( [id] => 7535643 [patent_doc_number] => 08049271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Power semiconductor device having a voltage sustaining layer with a terraced trench formation of floating islands' [patent_app_type] => utility [patent_app_number] => 12/772258 [patent_app_country] => US [patent_app_date] => 2010-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3664 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/049/08049271.pdf [firstpage_image] =>[orig_patent_app_number] => 12772258 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/772258
Power semiconductor device having a voltage sustaining layer with a terraced trench formation of floating islands May 2, 2010 Issued
Array ( [id] => 6483488 [patent_doc_number] => 20100258795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'ZINC OXIDE BASED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/756278 [patent_app_country] => US [patent_app_date] => 2010-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9395 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20100258795.pdf [firstpage_image] =>[orig_patent_app_number] => 12756278 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/756278
Method of manufacturing a zinc oxide (ZnO) based semiconductor device including performing a heat treatment of a contact metal layer on a p-type ZnO semiconductor layer in a reductive gas atmosphere Apr 7, 2010 Issued
Array ( [id] => 7480833 [patent_doc_number] => 20110248778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'DEVICES COMPRISING COLOSSAL MAGNETOCAPACITIVE MATERIALS AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 12/755940 [patent_app_country] => US [patent_app_date] => 2010-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7450 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20110248778.pdf [firstpage_image] =>[orig_patent_app_number] => 12755940 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/755940
Semiconductor devices including gate structures comprising colossal magnetocapacitive materials Apr 6, 2010 Issued
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