Search

Willis Little

Examiner (ID: 2267)

Most Active Art Unit
3203
Art Unit(s)
2103, 2401, 3203, 2403, 2107, 2406, 2899, 3616, 3643
Total Applications
2327
Issued Applications
2182
Pending Applications
48
Abandoned Applications
97

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9608932 [patent_doc_number] => 08786103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Stacked chips package having feed-through electrode connecting the first and second semiconductor components via an adhesive layer' [patent_app_type] => utility [patent_app_number] => 12/755515 [patent_app_country] => US [patent_app_date] => 2010-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 18951 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 430 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12755515 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/755515
Stacked chips package having feed-through electrode connecting the first and second semiconductor components via an adhesive layer Apr 6, 2010 Issued
Array ( [id] => 8071891 [patent_doc_number] => 20110241077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'INTEGRATED CIRCUIT 3D MEMORY ARRAY AND MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 12/755325 [patent_app_country] => US [patent_app_date] => 2010-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6241 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20110241077.pdf [firstpage_image] =>[orig_patent_app_number] => 12755325 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/755325
INTEGRATED CIRCUIT 3D MEMORY ARRAY AND MANUFACTURING METHOD Apr 5, 2010 Abandoned
Array ( [id] => 6264238 [patent_doc_number] => 20100252909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'Three-Dimensional Memory Devices' [patent_app_type] => utility [patent_app_number] => 12/754913 [patent_app_country] => US [patent_app_date] => 2010-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5624 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20100252909.pdf [firstpage_image] =>[orig_patent_app_number] => 12754913 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/754913
Three-Dimensional Memory Devices Apr 5, 2010 Abandoned
Array ( [id] => 6484680 [patent_doc_number] => 20100258907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/662189 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20100258907.pdf [firstpage_image] =>[orig_patent_app_number] => 12662189 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/662189
Semiconductor device and method of manufacturing the same Apr 4, 2010 Abandoned
Array ( [id] => 8070515 [patent_doc_number] => 20110241765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'PHASE QUANTUM BIT' [patent_app_type] => utility [patent_app_number] => 12/754194 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2483 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20110241765.pdf [firstpage_image] =>[orig_patent_app_number] => 12754194 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/754194
Phase quantum bit Apr 4, 2010 Issued
Array ( [id] => 8071819 [patent_doc_number] => 20110241114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'HIGH VOLTAGE MOS TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 12/753486 [patent_app_country] => US [patent_app_date] => 2010-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4238 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20110241114.pdf [firstpage_image] =>[orig_patent_app_number] => 12753486 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/753486
HIGH VOLTAGE MOS TRANSISTOR Apr 1, 2010 Abandoned
Array ( [id] => 8071821 [patent_doc_number] => 20110241113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'Dual Gate LDMOS Device with Reduced Capacitance' [patent_app_type] => utility [patent_app_number] => 12/752077 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9960 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20110241113.pdf [firstpage_image] =>[orig_patent_app_number] => 12752077 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/752077
Dual Gate LDMOS Device with Reduced Capacitance Mar 30, 2010 Abandoned
Array ( [id] => 7480457 [patent_doc_number] => 20110233513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'ENHANCED BONDING INTERFACES ON CARBON-BASED MATERIALS FOR NANOELECTRONIC DEVICES' [patent_app_type] => utility [patent_app_number] => 12/748542 [patent_app_country] => US [patent_app_date] => 2010-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5791 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20110233513.pdf [firstpage_image] =>[orig_patent_app_number] => 12748542 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/748542
ENHANCED BONDING INTERFACES ON CARBON-BASED MATERIALS FOR NANOELECTRONIC DEVICES Mar 28, 2010 Abandoned
Array ( [id] => 6321214 [patent_doc_number] => 20100244199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/749018 [patent_app_country] => US [patent_app_date] => 2010-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 24246 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20100244199.pdf [firstpage_image] =>[orig_patent_app_number] => 12749018 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/749018
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Mar 28, 2010 Abandoned
Array ( [id] => 6320941 [patent_doc_number] => 20100244141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'THRESHOLD ADJUSTMENT OF TRANSISTORS INCLUDING HIGH-K METAL GATE ELECTRODE STRUCTURES COMPRISING AN INTERMEDIATE ETCH STOP LAYER' [patent_app_type] => utility [patent_app_number] => 12/749112 [patent_app_country] => US [patent_app_date] => 2010-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8711 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20100244141.pdf [firstpage_image] =>[orig_patent_app_number] => 12749112 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/749112
Method for forming CMOS transistors having metal-containing gate electrodes formed on a high-K gate dielectric material Mar 28, 2010 Issued
Array ( [id] => 7480705 [patent_doc_number] => 20110233632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'SEMICONDUCTOR SEAL-RING STRUCTURE AND THE MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/749497 [patent_app_country] => US [patent_app_date] => 2010-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2282 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20110233632.pdf [firstpage_image] =>[orig_patent_app_number] => 12749497 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/749497
SEMICONDUCTOR SEAL-RING STRUCTURE AND THE MANUFACTURING METHOD THEREOF Mar 28, 2010 Abandoned
Array ( [id] => 4432576 [patent_doc_number] => 07897446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Method of forming a high electron mobility transistor hemt, utilizing self-aligned miniature field mitigating plate and protective dielectric layer' [patent_app_type] => utility [patent_app_number] => 12/659910 [patent_app_country] => US [patent_app_date] => 2010-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3736 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/897/07897446.pdf [firstpage_image] =>[orig_patent_app_number] => 12659910 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659910
Method of forming a high electron mobility transistor hemt, utilizing self-aligned miniature field mitigating plate and protective dielectric layer Mar 24, 2010 Issued
Array ( [id] => 6380951 [patent_doc_number] => 20100176083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'METHOD AND APPARATUS FOR REMOVING ADJACENT CONDUCTIVE AND NON-CONDUCTIVE MATERIALS OF A MICROELECTRONIC SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/731049 [patent_app_country] => US [patent_app_date] => 2010-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4269 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20100176083.pdf [firstpage_image] =>[orig_patent_app_number] => 12731049 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/731049
Method for removing metal layers formed outside an aperture of a BPSG layer utilizing multiple etching processes including electrochemical-mechanical polishing Mar 23, 2010 Issued
Array ( [id] => 6235527 [patent_doc_number] => 20100267231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'APPARATUS FOR UV DAMAGE REPAIR OF LOW K FILMS PRIOR TO COPPER BARRIER DEPOSITION' [patent_app_type] => utility [patent_app_number] => 12/726263 [patent_app_country] => US [patent_app_date] => 2010-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20100267231.pdf [firstpage_image] =>[orig_patent_app_number] => 12726263 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/726263
APPARATUS FOR UV DAMAGE REPAIR OF LOW K FILMS PRIOR TO COPPER BARRIER DEPOSITION Mar 16, 2010 Abandoned
Array ( [id] => 5931524 [patent_doc_number] => 20110210101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'PROCESSES FOR USING A PLASMA ARC TORCH TO OPERATE UPON AN INSULATION-COATED WORKPIECE' [patent_app_type] => utility [patent_app_number] => 12/715078 [patent_app_country] => US [patent_app_date] => 2010-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3614 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20110210101.pdf [firstpage_image] =>[orig_patent_app_number] => 12715078 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/715078
PROCESSES FOR USING A PLASMA ARC TORCH TO OPERATE UPON AN INSULATION-COATED WORKPIECE Feb 28, 2010 Abandoned
Array ( [id] => 6404981 [patent_doc_number] => 20100140079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'PREPARATION OF A PH SENSOR, THE PREPARED PH SENSOR, SYSTEM COMPRISING THE SAME AND MEASUREMENT USING THE SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/704864 [patent_app_country] => US [patent_app_date] => 2010-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3133 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20100140079.pdf [firstpage_image] =>[orig_patent_app_number] => 12704864 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/704864
PREPARATION OF A PH SENSOR, THE PREPARED PH SENSOR, SYSTEM COMPRISING THE SAME AND MEASUREMENT USING THE SYSTEM Feb 11, 2010 Abandoned
Array ( [id] => 6438622 [patent_doc_number] => 20100144109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'TRANSISTOR IN A SEMICONDUCTOR SUBSTRATE HAVING HIGH-CONCENTRATION SOURCE AND DRAIN REGION FORMED AT THE BOTTOM OF A TRENCH ADJACENT TO THE GATE ELECTRODE' [patent_app_type] => utility [patent_app_number] => 12/704402 [patent_app_country] => US [patent_app_date] => 2010-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3311 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20100144109.pdf [firstpage_image] =>[orig_patent_app_number] => 12704402 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/704402
Method of manufacturing a transistor in semiconductor device having a gate electrode located between the trenches formed in low-concentration regions of the source and drain regions including high-concentration regions formed at the bottom of the trenches Feb 10, 2010 Issued
Array ( [id] => 8397133 [patent_doc_number] => 08267489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-18 [patent_title] => 'Industrial machine assembly' [patent_app_type] => utility [patent_app_number] => 12/703437 [patent_app_country] => US [patent_app_date] => 2010-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2907 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12703437 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/703437
Industrial machine assembly Feb 9, 2010 Issued
Array ( [id] => 10004065 [patent_doc_number] => 09048164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-02 [patent_title] => 'Solid-state image sensing device containing electron multiplication function having N-type floating diffusion (FD) region formed within a P-type well region' [patent_app_type] => utility [patent_app_number] => 12/920144 [patent_app_country] => US [patent_app_date] => 2010-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4597 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12920144 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/920144
Solid-state image sensing device containing electron multiplication function having N-type floating diffusion (FD) region formed within a P-type well region Jan 26, 2010 Issued
Array ( [id] => 6106030 [patent_doc_number] => 20110186913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'SOLID STATE IMAGING DEVICE WITH ELECTRON MULTIPLYING FUNCTION' [patent_app_type] => utility [patent_app_number] => 12/920119 [patent_app_country] => US [patent_app_date] => 2010-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6264 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20110186913.pdf [firstpage_image] =>[orig_patent_app_number] => 12920119 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/920119
Solid state image device having a pair of overflow drains extends along the electron transfer direction at a boundary between channel region and channel stop isolation regions of the multiplication register Jan 26, 2010 Issued
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