Search

Willis Little

Examiner (ID: 2267)

Most Active Art Unit
3203
Art Unit(s)
2103, 2401, 3203, 2403, 2107, 2406, 2899, 3616, 3643
Total Applications
2327
Issued Applications
2182
Pending Applications
48
Abandoned Applications
97

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4863821 [patent_doc_number] => 20080142880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'METHOD FOR FABRICATING A POWER SEMICONDUCTOR DEVICE HAVING A VOLTAGE SUSTAINING LAYER WITH A TERRACED TRENCH FACILITATING FORMATION OF FLOATING ISLANDS' [patent_app_type] => utility [patent_app_number] => 11/950156 [patent_app_country] => US [patent_app_date] => 2007-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3637 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20080142880.pdf [firstpage_image] =>[orig_patent_app_number] => 11950156 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/950156
Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands Dec 3, 2007 Issued
Array ( [id] => 4937607 [patent_doc_number] => 20080074924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'NON-VOLATILE ELECTRICALLY ALTERABLE MEMORY CELLS FOR STORING MULTIPLE DATA' [patent_app_type] => utility [patent_app_number] => 11/946686 [patent_app_country] => US [patent_app_date] => 2007-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6466 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20080074924.pdf [firstpage_image] =>[orig_patent_app_number] => 11946686 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/946686
NON-VOLATILE ELECTRICALLY ALTERABLE MEMORY CELLS FOR STORING MULTIPLE DATA Nov 27, 2007 Abandoned
Array ( [id] => 125049 [patent_doc_number] => 07705899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Amplification type solid-state image pickup device driving method' [patent_app_type] => utility [patent_app_number] => 11/983013 [patent_app_country] => US [patent_app_date] => 2007-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7315 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/705/07705899.pdf [firstpage_image] =>[orig_patent_app_number] => 11983013 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/983013
Amplification type solid-state image pickup device driving method Nov 5, 2007 Issued
Array ( [id] => 9676770 [patent_doc_number] => 08815678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Method for fabricating a metal-insulator-metal (MIM) capacitor having capacitor dielectric layer formed by atomic layer deposition (ALD)' [patent_app_type] => utility [patent_app_number] => 11/928460 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 30 [patent_no_of_words] => 10427 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11928460 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/928460
Method for fabricating a metal-insulator-metal (MIM) capacitor having capacitor dielectric layer formed by atomic layer deposition (ALD) Oct 29, 2007 Issued
Array ( [id] => 4651627 [patent_doc_number] => 20080038883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Method for manufacturing semiconductor device utilizing recrystallized semiconductor film formed on an insulating film' [patent_app_type] => utility [patent_app_number] => 11/905934 [patent_app_country] => US [patent_app_date] => 2007-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5657 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20080038883.pdf [firstpage_image] =>[orig_patent_app_number] => 11905934 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/905934
Method for manufacturing semiconductor device utilizing recrystallized semiconductor film formed on an insulating film Oct 4, 2007 Abandoned
Array ( [id] => 4932988 [patent_doc_number] => 20080003763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'METHOD OF DEPOSITING SILICON WITH HIGH STEP COVERAGE' [patent_app_type] => utility [patent_app_number] => 11/853400 [patent_app_country] => US [patent_app_date] => 2007-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9002 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20080003763.pdf [firstpage_image] =>[orig_patent_app_number] => 11853400 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/853400
METHOD OF DEPOSITING SILICON WITH HIGH STEP COVERAGE Sep 10, 2007 Abandoned
Array ( [id] => 5293816 [patent_doc_number] => 20090008742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL AND ANTI-FUSE ELEMENT' [patent_app_type] => utility [patent_app_number] => 11/848390 [patent_app_country] => US [patent_app_date] => 2007-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6346 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20090008742.pdf [firstpage_image] =>[orig_patent_app_number] => 11848390 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/848390
SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL AND ANTI-FUSE ELEMENT Aug 30, 2007 Abandoned
Array ( [id] => 5165674 [patent_doc_number] => 20070287261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'TRENCH ISOLATION STRUCTURES FOR INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/844227 [patent_app_country] => US [patent_app_date] => 2007-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7569 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20070287261.pdf [firstpage_image] =>[orig_patent_app_number] => 11844227 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/844227
TRENCH ISOLATION STRUCTURES FOR INTEGRATED CIRCUITS Aug 22, 2007 Abandoned
Array ( [id] => 4909402 [patent_doc_number] => 20080020168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'SILICON ON INSULATOR STRUCTURE WITH A SINGLE CRYSTAL CZ SILICON DEVICE LAYER HAVING A REGION WHICH IS FREE OF AGGLOMERATED INTRINSIC POINT DEFECTS' [patent_app_type] => utility [patent_app_number] => 11/833730 [patent_app_country] => US [patent_app_date] => 2007-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 20138 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20080020168.pdf [firstpage_image] =>[orig_patent_app_number] => 11833730 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/833730
SILICON ON INSULATOR STRUCTURE WITH A SINGLE CRYSTAL CZ SILICON DEVICE LAYER HAVING A REGION WHICH IS FREE OF AGGLOMERATED INTRINSIC POINT DEFECTS Aug 2, 2007 Abandoned
Array ( [id] => 9869206 [patent_doc_number] => 08956978 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-02-17 [patent_title] => 'Semiconductor device, method for manufacturing semiconductor single-walled nanotubes, and approaches therefor' [patent_app_type] => utility [patent_app_number] => 11/830509 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5659 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11830509 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/830509
Semiconductor device, method for manufacturing semiconductor single-walled nanotubes, and approaches therefor Jul 29, 2007 Issued
Array ( [id] => 5046106 [patent_doc_number] => 20070264779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'METHODS FOR FORMING FLOATING GATE MEMORY STRUCTURES' [patent_app_type] => utility [patent_app_number] => 11/828557 [patent_app_country] => US [patent_app_date] => 2007-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2829 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20070264779.pdf [firstpage_image] =>[orig_patent_app_number] => 11828557 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/828557
METHODS FOR FORMING FLOATING GATE MEMORY STRUCTURES Jul 25, 2007 Abandoned
Array ( [id] => 5043741 [patent_doc_number] => 20070262412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Avoiding Field Oxide Gouging In Shallow Trench Isolation (STI) Regions' [patent_app_type] => utility [patent_app_number] => 11/781551 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2362 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20070262412.pdf [firstpage_image] =>[orig_patent_app_number] => 11781551 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/781551
Avoiding Field Oxide Gouging In Shallow Trench Isolation (STI) Regions Jul 22, 2007 Abandoned
Array ( [id] => 4932996 [patent_doc_number] => 20080003771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Semiconductor substrate and its fabrication method' [patent_app_type] => utility [patent_app_number] => 11/812490 [patent_app_country] => US [patent_app_date] => 2007-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 17257 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20080003771.pdf [firstpage_image] =>[orig_patent_app_number] => 11812490 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/812490
Method for fabricating a localize SOI in bulk silicon substrate including changing first trenches formed in the substrate into unclosed empty space by applying heat treatment Jun 18, 2007 Issued
Array ( [id] => 5123566 [patent_doc_number] => 20070235836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'METHOD OF FORMING A SHALLOW TRENCH ISOLATION STRUCTURE WITH REDUCED LEAKAGE CURRENT IN A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/763716 [patent_app_country] => US [patent_app_date] => 2007-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2154 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20070235836.pdf [firstpage_image] =>[orig_patent_app_number] => 11763716 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/763716
METHOD OF FORMING A SHALLOW TRENCH ISOLATION STRUCTURE WITH REDUCED LEAKAGE CURRENT IN A SEMICONDUCTOR DEVICE Jun 14, 2007 Abandoned
Array ( [id] => 5066647 [patent_doc_number] => 20070187748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'FLOATING GATE MEMORY STRUCTURES' [patent_app_type] => utility [patent_app_number] => 11/740698 [patent_app_country] => US [patent_app_date] => 2007-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2829 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20070187748.pdf [firstpage_image] =>[orig_patent_app_number] => 11740698 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/740698
FLOATING GATE MEMORY STRUCTURES Apr 25, 2007 Abandoned
Array ( [id] => 5110380 [patent_doc_number] => 20070194295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Semiconductor device of Group III nitride semiconductor having oxide protective insulating film formed on part of the active region' [patent_app_type] => utility [patent_app_number] => 11/785799 [patent_app_country] => US [patent_app_date] => 2007-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7612 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20070194295.pdf [firstpage_image] =>[orig_patent_app_number] => 11785799 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/785799
Semiconductor device of Group III nitride semiconductor having oxide protective insulating film formed on part of the active region Apr 19, 2007 Abandoned
Array ( [id] => 4740047 [patent_doc_number] => 20080233700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'Methods of forming integrated circuitry' [patent_app_type] => utility [patent_app_number] => 11/724784 [patent_app_country] => US [patent_app_date] => 2007-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6192 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20080233700.pdf [firstpage_image] =>[orig_patent_app_number] => 11724784 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/724784
Methods of forming integrated circuitry Mar 14, 2007 Abandoned
Array ( [id] => 5101345 [patent_doc_number] => 20070184607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Methods of forming integrated circuitry, and methods of forming dynamic random access memory cells' [patent_app_type] => utility [patent_app_number] => 11/724789 [patent_app_country] => US [patent_app_date] => 2007-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6193 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20070184607.pdf [firstpage_image] =>[orig_patent_app_number] => 11724789 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/724789
Methods of forming integrated circuitry, and methods of forming dynamic random access memory cells Mar 14, 2007 Abandoned
Array ( [id] => 5098624 [patent_doc_number] => 20070181884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Integrated circuitry, dynamic random access memory cells, and electronic systems' [patent_app_type] => utility [patent_app_number] => 11/724787 [patent_app_country] => US [patent_app_date] => 2007-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6192 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20070181884.pdf [firstpage_image] =>[orig_patent_app_number] => 11724787 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/724787
Integrated circuitry, dynamic random access memory cells, and electronic systems Mar 14, 2007 Abandoned
Array ( [id] => 5507840 [patent_doc_number] => 20090081047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'MULTI-ELEMENT BLADE WITH AERODYNAMIC PROFILES' [patent_app_type] => utility [patent_app_number] => 12/282861 [patent_app_country] => US [patent_app_date] => 2007-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4529 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20090081047.pdf [firstpage_image] =>[orig_patent_app_number] => 12282861 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/282861
Multi-element blade with aerodynamic profiles Mar 12, 2007 Issued
Menu