
Willis Little
Examiner (ID: 2267)
| Most Active Art Unit | 3203 |
| Art Unit(s) | 2103, 2401, 3203, 2403, 2107, 2406, 2899, 3616, 3643 |
| Total Applications | 2327 |
| Issued Applications | 2182 |
| Pending Applications | 48 |
| Abandoned Applications | 97 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7033737
[patent_doc_number] => 20050032247
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-10
[patent_title] => 'Method for making an integrated circuit comprising an active optical device having an energy band engineered superlattice'
[patent_app_type] => utility
[patent_app_number] => 10/936933
[patent_app_country] => US
[patent_app_date] => 2004-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 6901
[patent_no_of_claims] => 34
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0032/20050032247.pdf
[firstpage_image] =>[orig_patent_app_number] => 10936933
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/936933 | Method for making an integrated circuit comprising an active optical device having an energy band engineered superlattice | Sep 8, 2004 | Abandoned |
Array
(
[id] => 8446773
[patent_doc_number] => 08288828
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-10-16
[patent_title] => 'Via contact structure having dual silicide layers'
[patent_app_type] => utility
[patent_app_number] => 10/711298
[patent_app_country] => US
[patent_app_date] => 2004-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 4746
[patent_no_of_claims] => 10
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10711298
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/711298 | Via contact structure having dual silicide layers | Sep 8, 2004 | Issued |
Array
(
[id] => 946577
[patent_doc_number] => 06964909
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-11-15
[patent_title] => 'Method of forming a capacitor electrode having an interface layer of different chemical composition from a bulk layer'
[patent_app_type] => utility
[patent_app_number] => 10/931511
[patent_app_country] => US
[patent_app_date] => 2004-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4965
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/964/06964909.pdf
[firstpage_image] =>[orig_patent_app_number] => 10931511
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/931511 | Method of forming a capacitor electrode having an interface layer of different chemical composition from a bulk layer | Aug 31, 2004 | Issued |
Array
(
[id] => 7154660
[patent_doc_number] => 20050026355
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-03
[patent_title] => 'Capacitor structures'
[patent_app_type] => utility
[patent_app_number] => 10/931570
[patent_app_country] => US
[patent_app_date] => 2004-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5712
[patent_no_of_claims] => 20
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[patent_words_short_claim] => 0
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0026/20050026355.pdf
[firstpage_image] =>[orig_patent_app_number] => 10931570
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/931570 | Capacitor structures | Aug 30, 2004 | Issued |
Array
(
[id] => 6991036
[patent_doc_number] => 20050090073
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => 'MOS transistor having improved total radiation-induced leakage current'
[patent_app_type] => utility
[patent_app_number] => 10/929107
[patent_app_country] => US
[patent_app_date] => 2004-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 2420
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0090/20050090073.pdf
[firstpage_image] =>[orig_patent_app_number] => 10929107
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/929107 | MOS transistor having improved total radiation-induced leakage current | Aug 26, 2004 | Abandoned |
Array
(
[id] => 6991010
[patent_doc_number] => 20050090047
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => 'Method of making a MOS transistor having improved total radiation-induced leakage current'
[patent_app_type] => utility
[patent_app_number] => 10/929106
[patent_app_country] => US
[patent_app_date] => 2004-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 2448
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0090/20050090047.pdf
[firstpage_image] =>[orig_patent_app_number] => 10929106
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/929106 | Method of making a MOS transistor having improved total radiation-induced leakage current | Aug 26, 2004 | Abandoned |
Array
(
[id] => 5897452
[patent_doc_number] => 20060042685
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-02
[patent_title] => 'Electronic devices having a charge transport layer that has defined triplet energy level'
[patent_app_type] => utility
[patent_app_number] => 10/925764
[patent_app_country] => US
[patent_app_date] => 2004-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 8322
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0042/20060042685.pdf
[firstpage_image] =>[orig_patent_app_number] => 10925764
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/925764 | Electronic devices having a charge transport layer that has defined triplet energy level | Aug 24, 2004 | Abandoned |
Array
(
[id] => 7120329
[patent_doc_number] => 20050012158
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-20
[patent_title] => 'Locos trench isolation structure'
[patent_app_type] => utility
[patent_app_number] => 10/899609
[patent_app_country] => US
[patent_app_date] => 2004-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6041
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0012/20050012158.pdf
[firstpage_image] =>[orig_patent_app_number] => 10899609
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/899609 | Locos trench isolation structure | Jul 26, 2004 | Abandoned |
Array
(
[id] => 425515
[patent_doc_number] => 07271498
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-18
[patent_title] => 'Bump electrodes having multiple under ball metallurgy (UBM) layers'
[patent_app_type] => utility
[patent_app_number] => 10/710419
[patent_app_country] => US
[patent_app_date] => 2004-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 3917
[patent_no_of_claims] => 14
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/271/07271498.pdf
[firstpage_image] =>[orig_patent_app_number] => 10710419
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/710419 | Bump electrodes having multiple under ball metallurgy (UBM) layers | Jul 8, 2004 | Issued |
Array
(
[id] => 7250079
[patent_doc_number] => 20040238889
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-02
[patent_title] => 'Process for making a silicon-on-insulator ledge and structures achieved thereby'
[patent_app_type] => new
[patent_app_number] => 10/880896
[patent_app_country] => US
[patent_app_date] => 2004-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 10414
[patent_no_of_claims] => 25
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0238/20040238889.pdf
[firstpage_image] =>[orig_patent_app_number] => 10880896
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/880896 | Process for making a silicon-on-insulator ledge and structures achieved thereby | Jun 29, 2004 | Abandoned |
Array
(
[id] => 142629
[patent_doc_number] => 07687854
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-30
[patent_title] => 'Transistor in a semiconductor substrate having high-concentration source and drain region formed at the bottom of a trench adjacent to the gate electrode'
[patent_app_type] => utility
[patent_app_number] => 10/876729
[patent_app_country] => US
[patent_app_date] => 2004-06-28
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/687/07687854.pdf
[firstpage_image] =>[orig_patent_app_number] => 10876729
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/876729 | Transistor in a semiconductor substrate having high-concentration source and drain region formed at the bottom of a trench adjacent to the gate electrode | Jun 27, 2004 | Issued |
Array
(
[id] => 7317878
[patent_doc_number] => 20040224476
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-11
[patent_title] => 'Semiconductor integrated circuit device'
[patent_app_type] => new
[patent_app_number] => 10/866018
[patent_app_country] => US
[patent_app_date] => 2004-06-14
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0224/20040224476.pdf
[firstpage_image] =>[orig_patent_app_number] => 10866018
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/866018 | Semiconductor integrated circuit device | Jun 13, 2004 | Abandoned |
Array
(
[id] => 419099
[patent_doc_number] => 07276774
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-02
[patent_title] => 'Trench isolation structures for integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 10/867826
[patent_app_country] => US
[patent_app_date] => 2004-06-14
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[pdf_file] => patents/07/276/07276774.pdf
[firstpage_image] =>[orig_patent_app_number] => 10867826
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/867826 | Trench isolation structures for integrated circuits | Jun 13, 2004 | Issued |
Array
(
[id] => 6952016
[patent_doc_number] => 20050227110
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-13
[patent_title] => 'Organic electroluminescent element'
[patent_app_type] => utility
[patent_app_number] => 10/856160
[patent_app_country] => US
[patent_app_date] => 2004-05-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0227/20050227110.pdf
[firstpage_image] =>[orig_patent_app_number] => 10856160
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/856160 | Organic electroluminescent element | May 27, 2004 | Abandoned |
Array
(
[id] => 338382
[patent_doc_number] => 07504727
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-17
[patent_title] => 'Semiconductor interconnect structure utilizing a porous dielectric material as an etch stop layer between adjacent non-porous dielectric materials'
[patent_app_type] => utility
[patent_app_number] => 10/845718
[patent_app_country] => US
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[pdf_file] => patents/07/504/07504727.pdf
[firstpage_image] =>[orig_patent_app_number] => 10845718
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/845718 | Semiconductor interconnect structure utilizing a porous dielectric material as an etch stop layer between adjacent non-porous dielectric materials | May 13, 2004 | Issued |
Array
(
[id] => 7273531
[patent_doc_number] => 20040232982
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-25
[patent_title] => 'RF front-end module for wireless communication devices'
[patent_app_type] => new
[patent_app_number] => 10/843409
[patent_app_country] => US
[patent_app_date] => 2004-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[pdf_file] => publications/A1/0232/20040232982.pdf
[firstpage_image] =>[orig_patent_app_number] => 10843409
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/843409 | RF front-end module for wireless communication devices | May 9, 2004 | Abandoned |
Array
(
[id] => 7411550
[patent_doc_number] => 20040207011
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-21
[patent_title] => 'Semiconductor device, semiconductor storage device and production methods therefor'
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[patent_app_date] => 2004-04-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/484078 | Semiconductor device, semiconductor storage device and production methods therefor | Apr 28, 2004 | Abandoned |
Array
(
[id] => 7451208
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[patent_issue_date] => 2004-10-07
[patent_title] => 'Reduction of noise, and optimization of magnetic field sensitivity and electrical properties in magnetic tunnel junction devices'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/824959 | Reduction of noise, and optimization of magnetic field sensitivity and electrical properties in magnetic tunnel junction devices | Apr 13, 2004 | Abandoned |
Array
(
[id] => 7423791
[patent_doc_number] => 20040229459
[patent_country] => US
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[patent_issue_date] => 2004-11-18
[patent_title] => 'Integration of annealing capability into metal deposition or CMP tool'
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[patent_app_number] => 10/810735
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10810735
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/810735 | Integration of annealing capability into metal deposition or CMP tool | Mar 24, 2004 | Abandoned |
Array
(
[id] => 5239721
[patent_doc_number] => 20070018212
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-25
[patent_title] => 'Photodiode array and production method thereof, and radiation detector'
[patent_app_type] => utility
[patent_app_number] => 10/550689
[patent_app_country] => US
[patent_app_date] => 2004-03-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0018/20070018212.pdf
[firstpage_image] =>[orig_patent_app_number] => 10550689
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/550689 | Photodiode array and radiation detector having depressions of predetermined depth formed in regions corresponding to the regions where the photodiodes are formed in the semiconductor substrate | Mar 24, 2004 | Issued |