Search

Willis Little

Examiner (ID: 2267)

Most Active Art Unit
3203
Art Unit(s)
2103, 2401, 3203, 2403, 2107, 2406, 2899, 3616, 3643
Total Applications
2327
Issued Applications
2182
Pending Applications
48
Abandoned Applications
97

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 64938 [patent_doc_number] => 07759740 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-07-20 [patent_title] => 'Deep well regions for routing body-bias voltage to mosfets in surface well regions having separation wells of p-type between the segmented deep n wells' [patent_app_type] => utility [patent_app_number] => 10/808225 [patent_app_country] => US [patent_app_date] => 2004-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2549 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/759/07759740.pdf [firstpage_image] =>[orig_patent_app_number] => 10808225 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/808225
Deep well regions for routing body-bias voltage to mosfets in surface well regions having separation wells of p-type between the segmented deep n wells Mar 22, 2004 Issued
10/801789 Dual floating gates non-volatile electrically alterable memory cell for storing multiple data Mar 15, 2004 Abandoned
Array ( [id] => 7162027 [patent_doc_number] => 20050199918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Optimized trench power MOSFET with integrated schottky diode' [patent_app_type] => utility [patent_app_number] => 10/801499 [patent_app_country] => US [patent_app_date] => 2004-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3544 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20050199918.pdf [firstpage_image] =>[orig_patent_app_number] => 10801499 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/801499
Optimized trench power MOSFET with integrated schottky diode Mar 14, 2004 Abandoned
Array ( [id] => 7407508 [patent_doc_number] => 20040227236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Semiconductor device, electronic device, electronic apparatus, and methods for manufacturing carrier substrate, semiconductor device, and electronic device' [patent_app_type] => new [patent_app_number] => 10/801089 [patent_app_country] => US [patent_app_date] => 2004-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7900 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20040227236.pdf [firstpage_image] =>[orig_patent_app_number] => 10801089 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/801089
Semiconductor device, electronic device, electronic apparatus, and methods for manufacturing carrier substrate, semiconductor device, and electronic device Mar 14, 2004 Abandoned
Array ( [id] => 432241 [patent_doc_number] => 07265014 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-04 [patent_title] => 'Avoiding field oxide gouging in shallow trench isolation (STI) regions' [patent_app_type] => utility [patent_app_number] => 10/799413 [patent_app_country] => US [patent_app_date] => 2004-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2415 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/265/07265014.pdf [firstpage_image] =>[orig_patent_app_number] => 10799413 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/799413
Avoiding field oxide gouging in shallow trench isolation (STI) regions Mar 11, 2004 Issued
Array ( [id] => 944093 [patent_doc_number] => 06967146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Isolation region forming methods' [patent_app_type] => utility [patent_app_number] => 10/799794 [patent_app_country] => US [patent_app_date] => 2004-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 4674 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967146.pdf [firstpage_image] =>[orig_patent_app_number] => 10799794 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/799794
Isolation region forming methods Mar 10, 2004 Issued
Array ( [id] => 7673296 [patent_doc_number] => 20040180483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Method of manufacturing CMOS transistor with LDD structure' [patent_app_type] => new [patent_app_number] => 10/795705 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5930 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20040180483.pdf [firstpage_image] =>[orig_patent_app_number] => 10795705 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/795705
Method of manufacturing CMOS transistor with LDD structure Mar 7, 2004 Abandoned
Array ( [id] => 7375298 [patent_doc_number] => 20040178429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Thin film transistor and method for manufacturing same' [patent_app_type] => new [patent_app_number] => 10/793845 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8728 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20040178429.pdf [firstpage_image] =>[orig_patent_app_number] => 10793845 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/793845
Thin film transistor and method for manufacturing same Mar 7, 2004 Abandoned
Array ( [id] => 6944855 [patent_doc_number] => 20050196904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => ' Aerodynamic memory module cover' [patent_app_type] => utility [patent_app_number] => 10/794129 [patent_app_country] => US [patent_app_date] => 2004-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 628 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20050196904.pdf [firstpage_image] =>[orig_patent_app_number] => 10794129 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/794129
Aerodynamic memory module cover Mar 4, 2004 Abandoned
Array ( [id] => 6942650 [patent_doc_number] => 20050194698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Integrated circuit package with keep-out zone overlapping undercut zone' [patent_app_type] => utility [patent_app_number] => 10/794109 [patent_app_country] => US [patent_app_date] => 2004-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20050194698.pdf [firstpage_image] =>[orig_patent_app_number] => 10794109 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/794109
Integrated circuit package with keep-out zone overlapping undercut zone Mar 2, 2004 Abandoned
Array ( [id] => 7457427 [patent_doc_number] => 20040165459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Array architecture and process flow of nonvolatile memory devices for mass storage applications' [patent_app_type] => new [patent_app_number] => 10/790579 [patent_app_country] => US [patent_app_date] => 2004-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4421 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20040165459.pdf [firstpage_image] =>[orig_patent_app_number] => 10790579 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/790579
Array architecture and process flow of nonvolatile memory devices for mass storage applications Feb 29, 2004 Abandoned
Array ( [id] => 7184197 [patent_doc_number] => 20040203213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Method for manufacturing an MOS varactor' [patent_app_type] => new [patent_app_number] => 10/789905 [patent_app_country] => US [patent_app_date] => 2004-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2129 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20040203213.pdf [firstpage_image] =>[orig_patent_app_number] => 10789905 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/789905
Method for manufacturing an MOS varactor Feb 26, 2004 Abandoned
Array ( [id] => 7465643 [patent_doc_number] => 20040166667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/782783 [patent_app_country] => US [patent_app_date] => 2004-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6595 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20040166667.pdf [firstpage_image] =>[orig_patent_app_number] => 10782783 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/782783
Method for manufacturing vias between conductive patterns utilizing etching mask patterns formed on the conductive patterns Feb 22, 2004 Issued
Array ( [id] => 7136970 [patent_doc_number] => 20050181618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Polymer via etching process' [patent_app_type] => utility [patent_app_number] => 10/781353 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3807 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20050181618.pdf [firstpage_image] =>[orig_patent_app_number] => 10781353 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/781353
Polymer via etching process Feb 16, 2004 Abandoned
Array ( [id] => 7132966 [patent_doc_number] => 20050179111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Semiconductor device with low resistive path barrier' [patent_app_type] => utility [patent_app_number] => 10/779379 [patent_app_country] => US [patent_app_date] => 2004-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2978 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20050179111.pdf [firstpage_image] =>[orig_patent_app_number] => 10779379 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/779379
Semiconductor device with low resistive path barrier Feb 11, 2004 Abandoned
Array ( [id] => 712195 [patent_doc_number] => 07057239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Semiconductor device allowing modulation of a gain coefficient and a logic circuit provided with the same' [patent_app_type] => utility [patent_app_number] => 10/769819 [patent_app_country] => US [patent_app_date] => 2004-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/057/07057239.pdf [firstpage_image] =>[orig_patent_app_number] => 10769819 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/769819
Semiconductor device allowing modulation of a gain coefficient and a logic circuit provided with the same Feb 2, 2004 Issued
Array ( [id] => 681058 [patent_doc_number] => 07084455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Power semiconductor device having a voltage sustaining region that includes terraced trench with continuous doped columns formed in an epitaxial layer' [patent_app_type] => utility [patent_app_number] => 10/770045 [patent_app_country] => US [patent_app_date] => 2004-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3899 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084455.pdf [firstpage_image] =>[orig_patent_app_number] => 10770045 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/770045
Power semiconductor device having a voltage sustaining region that includes terraced trench with continuous doped columns formed in an epitaxial layer Feb 1, 2004 Issued
Array ( [id] => 190893 [patent_doc_number] => 07642204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Methods of forming fluorine doped insulating materials' [patent_app_type] => utility [patent_app_number] => 10/769430 [patent_app_country] => US [patent_app_date] => 2004-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2304 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/642/07642204.pdf [firstpage_image] =>[orig_patent_app_number] => 10769430 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/769430
Methods of forming fluorine doped insulating materials Jan 29, 2004 Issued
Array ( [id] => 7328772 [patent_doc_number] => 20040129933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Pixel current driver for organic light emitting diode displays' [patent_app_type] => new [patent_app_number] => 10/468319 [patent_app_country] => US [patent_app_date] => 2004-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4292 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20040129933.pdf [firstpage_image] =>[orig_patent_app_number] => 10468319 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/468319
Pixel current driver for organic light emitting diode displays Jan 22, 2004 Abandoned
Array ( [id] => 7260234 [patent_doc_number] => 20040150065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Field oxide profile of an isolation region associated with a contact structure of a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/761691 [patent_app_country] => US [patent_app_date] => 2004-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3487 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20040150065.pdf [firstpage_image] =>[orig_patent_app_number] => 10761691 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/761691
Field oxide profile of an isolation region associated with a contact structure of a semiconductor device Jan 19, 2004 Abandoned
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