Search

Willis Little

Examiner (ID: 13674)

Most Active Art Unit
3203
Art Unit(s)
2899, 3643, 2107, 2403, 2406, 3203, 3616, 2401, 2103
Total Applications
2327
Issued Applications
2182
Pending Applications
48
Abandoned Applications
97

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18827725 [patent_doc_number] => 11843016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Image sensor [patent_app_type] => utility [patent_app_number] => 17/402665 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 25 [patent_no_of_words] => 8756 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17402665 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/402665
Image sensor Aug 15, 2021 Issued
Array ( [id] => 17247033 [patent_doc_number] => 20210366778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => GATE STACK TREATMENT [patent_app_type] => utility [patent_app_number] => 17/397529 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397529 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/397529
Gate stack treatment Aug 8, 2021 Issued
Array ( [id] => 18178053 [patent_doc_number] => 20230038782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => MEMORY DEVICE AND METHOD FOR FORMING A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/394757 [patent_app_country] => US [patent_app_date] => 2021-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17394757 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/394757
Ferroelectric memory device with a metal layer having a crystal orientation for improving ferroelectric polarization and method for forming the ferroelectric memory device Aug 4, 2021 Issued
Array ( [id] => 17536659 [patent_doc_number] => 20220115268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => HIGH SPEED, HIGH DENSITY, LOW POWER DIE INTERCONNECT SYSTEM [patent_app_type] => utility [patent_app_number] => 17/380643 [patent_app_country] => US [patent_app_date] => 2021-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17380643 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/380643
HIGH SPEED, HIGH DENSITY, LOW POWER DIE INTERCONNECT SYSTEM Jul 19, 2021 Pending
Array ( [id] => 18952574 [patent_doc_number] => 11895894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Display apparatus including the bezel layer [patent_app_type] => utility [patent_app_number] => 17/369184 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 11610 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369184 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369184
Display apparatus including the bezel layer Jul 6, 2021 Issued
Array ( [id] => 19495740 [patent_doc_number] => 12114479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Three-dimensional memory arrays with layer selector transistors [patent_app_type] => utility [patent_app_number] => 17/368329 [patent_app_country] => US [patent_app_date] => 2021-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 19274 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17368329 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/368329
Three-dimensional memory arrays with layer selector transistors Jul 5, 2021 Issued
Array ( [id] => 18481170 [patent_doc_number] => 11694924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Semiconductor device having contact plug [patent_app_type] => utility [patent_app_number] => 17/365911 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 6917 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365911 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/365911
Semiconductor device having contact plug Jun 30, 2021 Issued
Array ( [id] => 18263177 [patent_doc_number] => 11610886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods [patent_app_type] => utility [patent_app_number] => 17/365682 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365682 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/365682
Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods Jun 30, 2021 Issued
Array ( [id] => 18105472 [patent_doc_number] => 11545369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Method of fastening a semiconductor chip on a lead frame, and electronic component [patent_app_type] => utility [patent_app_number] => 17/361435 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 9901 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361435 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/361435
Method of fastening a semiconductor chip on a lead frame, and electronic component Jun 28, 2021 Issued
Array ( [id] => 18507613 [patent_doc_number] => 11705441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Manufacturing method of micro LED display device [patent_app_type] => utility [patent_app_number] => 17/359679 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 8192 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359679 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359679
Manufacturing method of micro LED display device Jun 27, 2021 Issued
Array ( [id] => 17855353 [patent_doc_number] => 20220285396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => FERROELECTRIC MEMORY DEVICE, MANUFACTURING METHOD OF THE FERROELECTRIC MEMORY DEVICE AND SEMICONDUCTOR CHIP [patent_app_type] => utility [patent_app_number] => 17/352339 [patent_app_country] => US [patent_app_date] => 2021-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17080 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17352339 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/352339
Ferroelectric memory device, manufacturing method of the ferroelectric memory device and semiconductor chip Jun 19, 2021 Issued
Array ( [id] => 18529840 [patent_doc_number] => 11716857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Semiconductor memory device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/351121 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 8345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351121 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/351121
Semiconductor memory device and manufacturing method thereof Jun 16, 2021 Issued
Array ( [id] => 18999271 [patent_doc_number] => 11916127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Multi-layer electrode to improve performance of ferroelectric memory device [patent_app_type] => utility [patent_app_number] => 17/349273 [patent_app_country] => US [patent_app_date] => 2021-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 8505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17349273 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/349273
Multi-layer electrode to improve performance of ferroelectric memory device Jun 15, 2021 Issued
Array ( [id] => 18387429 [patent_doc_number] => 11658224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Split gate memory device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/347848 [patent_app_country] => US [patent_app_date] => 2021-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 4313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17347848 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/347848
Split gate memory device and method of fabricating the same Jun 14, 2021 Issued
Array ( [id] => 19137375 [patent_doc_number] => 11972342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Image sensor architecture [patent_app_type] => utility [patent_app_number] => 17/346738 [patent_app_country] => US [patent_app_date] => 2021-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346738 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/346738
Image sensor architecture Jun 13, 2021 Issued
Array ( [id] => 17933382 [patent_doc_number] => 20220328508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => BOTTOM-ELECTRODE INTERFACE STRUCTURE FOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/346701 [patent_app_country] => US [patent_app_date] => 2021-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346701 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/346701
Bottom-electrode interface structure for memory Jun 13, 2021 Issued
Array ( [id] => 18690018 [patent_doc_number] => 11785779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Method for forming a semiconductor memory structure using a liner layer as an etch stop [patent_app_type] => utility [patent_app_number] => 17/345499 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 59 [patent_no_of_words] => 8270 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345499 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/345499
Method for forming a semiconductor memory structure using a liner layer as an etch stop Jun 10, 2021 Issued
Array ( [id] => 17332492 [patent_doc_number] => 11222960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Semiconductor device structures with composite spacers and fabrication methods thereof [patent_app_type] => utility [patent_app_number] => 17/345185 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 12524 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345185 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/345185
Semiconductor device structures with composite spacers and fabrication methods thereof Jun 10, 2021 Issued
Array ( [id] => 17855352 [patent_doc_number] => 20220285395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => HIGH SELECTIVITY ISOLATION STRUCTURE FOR IMPROVING EFFECTIVENESS OF 3D MEMORY FABRICATION [patent_app_type] => utility [patent_app_number] => 17/333300 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17333300 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/333300
High selectivity isolation structure for improving effectiveness of 3D memory fabrication May 27, 2021 Issued
Array ( [id] => 18579121 [patent_doc_number] => 11735661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Method of fabricating semiconductor device having epitaxial structure [patent_app_type] => utility [patent_app_number] => 17/330443 [patent_app_country] => US [patent_app_date] => 2021-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5169 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17330443 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/330443
Method of fabricating semiconductor device having epitaxial structure May 25, 2021 Issued
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