Search

Willis Little

Examiner (ID: 13674)

Most Active Art Unit
3203
Art Unit(s)
2899, 3643, 2107, 2403, 2406, 3203, 3616, 2401, 2103
Total Applications
2327
Issued Applications
2182
Pending Applications
48
Abandoned Applications
97

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5622983 [patent_doc_number] => 20060261488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Wafer level electro-optical simiconductor manufacture fabrication mechanism and a method for the same' [patent_app_type] => utility [patent_app_number] => 11/492816 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2050 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20060261488.pdf [firstpage_image] =>[orig_patent_app_number] => 11492816 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/492816
Wafer level electro-optical simiconductor manufacture fabrication mechanism and a method for the same Jul 25, 2006 Abandoned
Array ( [id] => 4619662 [patent_doc_number] => 07999383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'High speed, high density, low power die interconnect system' [patent_app_type] => utility [patent_app_number] => 11/459081 [patent_app_country] => US [patent_app_date] => 2006-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 32 [patent_no_of_words] => 19514 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/999/07999383.pdf [firstpage_image] =>[orig_patent_app_number] => 11459081 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/459081
High speed, high density, low power die interconnect system Jul 20, 2006 Issued
Array ( [id] => 574147 [patent_doc_number] => 07462916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Semiconductor devices having torsional stresses' [patent_app_type] => utility [patent_app_number] => 11/458461 [patent_app_country] => US [patent_app_date] => 2006-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 27 [patent_no_of_words] => 5339 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/462/07462916.pdf [firstpage_image] =>[orig_patent_app_number] => 11458461 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/458461
Semiconductor devices having torsional stresses Jul 18, 2006 Issued
Array ( [id] => 113907 [patent_doc_number] => 07714443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Pad structure design with reduced density' [patent_app_type] => utility [patent_app_number] => 11/458501 [patent_app_country] => US [patent_app_date] => 2006-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/714/07714443.pdf [firstpage_image] =>[orig_patent_app_number] => 11458501 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/458501
Pad structure design with reduced density Jul 18, 2006 Issued
Array ( [id] => 5098759 [patent_doc_number] => 20070182019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Semiconductor device and manufacturing method for the same' [patent_app_type] => utility [patent_app_number] => 11/487421 [patent_app_country] => US [patent_app_date] => 2006-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11966 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20070182019.pdf [firstpage_image] =>[orig_patent_app_number] => 11487421 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/487421
Semiconductor device having a bump formed over an electrode pad Jul 16, 2006 Issued
Array ( [id] => 233144 [patent_doc_number] => 07598571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'Semiconductor device having vertical channels and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/457781 [patent_app_country] => US [patent_app_date] => 2006-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 38 [patent_no_of_words] => 5734 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/598/07598571.pdf [firstpage_image] =>[orig_patent_app_number] => 11457781 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/457781
Semiconductor device having vertical channels and method of manufacturing the same Jul 13, 2006 Issued
Array ( [id] => 485522 [patent_doc_number] => 07217616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Non-volatile memory cell and method of forming the same' [patent_app_type] => utility [patent_app_number] => 11/481043 [patent_app_country] => US [patent_app_date] => 2006-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 2297 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/217/07217616.pdf [firstpage_image] =>[orig_patent_app_number] => 11481043 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/481043
Non-volatile memory cell and method of forming the same Jul 5, 2006 Issued
Array ( [id] => 4992243 [patent_doc_number] => 20070007587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Diode' [patent_app_type] => utility [patent_app_number] => 11/428741 [patent_app_country] => US [patent_app_date] => 2006-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3347 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20070007587.pdf [firstpage_image] =>[orig_patent_app_number] => 11428741 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/428741
Diode Jul 4, 2006 Abandoned
Array ( [id] => 93122 [patent_doc_number] => 07732890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Integrated circuit with high voltage junction structure' [patent_app_type] => utility [patent_app_number] => 11/426941 [patent_app_country] => US [patent_app_date] => 2006-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1425 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/732/07732890.pdf [firstpage_image] =>[orig_patent_app_number] => 11426941 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/426941
Integrated circuit with high voltage junction structure Jun 27, 2006 Issued
Array ( [id] => 5832243 [patent_doc_number] => 20060244073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'FABRICATION OF AN EEPROM CELL WITH SiGe SOURCE/DRAIN REGIONS' [patent_app_type] => utility [patent_app_number] => 11/426371 [patent_app_country] => US [patent_app_date] => 2006-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3503 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20060244073.pdf [firstpage_image] =>[orig_patent_app_number] => 11426371 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/426371
FABRICATION OF AN EEPROM CELL WITH SiGe SOURCE/DRAIN REGIONS Jun 25, 2006 Abandoned
Array ( [id] => 5642830 [patent_doc_number] => 20060281285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'Semiconductor device and a method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/451422 [patent_app_country] => US [patent_app_date] => 2006-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13826 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20060281285.pdf [firstpage_image] =>[orig_patent_app_number] => 11451422 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/451422
Semiconductor device and a method of manufacturing the same Jun 12, 2006 Issued
Array ( [id] => 5854622 [patent_doc_number] => 20060226555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/449814 [patent_app_country] => US [patent_app_date] => 2006-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 19613 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20060226555.pdf [firstpage_image] =>[orig_patent_app_number] => 11449814 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/449814
Semiconductor device and manufacturing method thereof Jun 8, 2006 Issued
Array ( [id] => 5916440 [patent_doc_number] => 20060237745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Super lattice modification of overlying transistor' [patent_app_type] => utility [patent_app_number] => 11/450806 [patent_app_country] => US [patent_app_date] => 2006-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8241 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20060237745.pdf [firstpage_image] =>[orig_patent_app_number] => 11450806 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/450806
Super lattice modification of overlying transistor Jun 7, 2006 Issued
Array ( [id] => 5008203 [patent_doc_number] => 20070278680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'METHOD AND DEVICE FOR CONCENTRATING LIGHT IN OPTOELECTRONIC DEVICES USING RESONANT CAVITY MODES' [patent_app_type] => utility [patent_app_number] => 11/422351 [patent_app_country] => US [patent_app_date] => 2006-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8013 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20070278680.pdf [firstpage_image] =>[orig_patent_app_number] => 11422351 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/422351
Method and device for concentrating light in optoelectronic devices using resonant cavity modes Jun 5, 2006 Issued
Array ( [id] => 5088937 [patent_doc_number] => 20070228576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'ISOLATING CHIP-TO-CHIP CONTACT' [patent_app_type] => utility [patent_app_number] => 11/422551 [patent_app_country] => US [patent_app_date] => 2006-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 123 [patent_figures_cnt] => 123 [patent_no_of_words] => 47578 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20070228576.pdf [firstpage_image] =>[orig_patent_app_number] => 11422551 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/422551
Isolating chip-to-chip contact Jun 5, 2006 Issued
Array ( [id] => 5008107 [patent_doc_number] => 20070278584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'SEMICONDUCTOR DEVICE FABRICATED USING A METAL MICROSTRUCTURE CONTROL PROCESS' [patent_app_type] => utility [patent_app_number] => 11/421671 [patent_app_country] => US [patent_app_date] => 2006-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5099 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20070278584.pdf [firstpage_image] =>[orig_patent_app_number] => 11421671 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/421671
Semiconductor device fabricated using a metal microstructure control process May 31, 2006 Issued
Array ( [id] => 152760 [patent_doc_number] => 07679159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-16 [patent_title] => 'Solid state imaging device and solid state imaging element' [patent_app_type] => utility [patent_app_number] => 11/444312 [patent_app_country] => US [patent_app_date] => 2006-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 14165 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/679/07679159.pdf [firstpage_image] =>[orig_patent_app_number] => 11444312 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/444312
Solid state imaging device and solid state imaging element May 31, 2006 Issued
Array ( [id] => 5697538 [patent_doc_number] => 20060214222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Power semiconductor devices and methods of manufacture' [patent_app_type] => utility [patent_app_number] => 11/445111 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 73 [patent_figures_cnt] => 73 [patent_no_of_words] => 30657 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20060214222.pdf [firstpage_image] =>[orig_patent_app_number] => 11445111 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/445111
Power semiconductor devices and methods of manufacture May 30, 2006 Issued
Array ( [id] => 4577287 [patent_doc_number] => 07855422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-21 [patent_title] => 'Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process' [patent_app_type] => utility [patent_app_number] => 11/444852 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3722 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/855/07855422.pdf [firstpage_image] =>[orig_patent_app_number] => 11444852 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/444852
Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process May 30, 2006 Issued
Array ( [id] => 5138984 [patent_doc_number] => 20070001200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/444271 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4021 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20070001200.pdf [firstpage_image] =>[orig_patent_app_number] => 11444271 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/444271
Semiconductor device and method of manufacturing the same May 30, 2006 Issued
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