Willis Little
Examiner (ID: 13674)
Most Active Art Unit | 3203 |
Art Unit(s) | 2899, 3643, 2107, 2403, 2406, 3203, 3616, 2401, 2103 |
Total Applications | 2327 |
Issued Applications | 2182 |
Pending Applications | 48 |
Abandoned Applications | 97 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 770216
[patent_doc_number] => 07005721
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-28
[patent_title] => 'RF passive circuit and RF amplifier with via-holes'
[patent_app_type] => utility
[patent_app_number] => 10/731821
[patent_app_country] => US
[patent_app_date] => 2003-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 29
[patent_no_of_words] => 6795
[patent_no_of_claims] => 8
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[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/005/07005721.pdf
[firstpage_image] =>[orig_patent_app_number] => 10731821
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/731821 | RF passive circuit and RF amplifier with via-holes | Dec 8, 2003 | Issued |
Array
(
[id] => 6969659
[patent_doc_number] => 20050035369
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-17
[patent_title] => 'Structure and method of forming integrated circuits utilizing strained channel transistors'
[patent_app_type] => utility
[patent_app_number] => 10/729092
[patent_app_country] => US
[patent_app_date] => 2003-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5380
[patent_no_of_claims] => 77
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0035/20050035369.pdf
[firstpage_image] =>[orig_patent_app_number] => 10729092
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/729092 | Structure and method of forming integrated circuits utilizing strained channel transistors | Dec 4, 2003 | Abandoned |
Array
(
[id] => 1037869
[patent_doc_number] => 06873021
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-29
[patent_title] => 'MOS transistors having higher drain current without reduced breakdown voltage'
[patent_app_type] => utility
[patent_app_number] => 10/725641
[patent_app_country] => US
[patent_app_date] => 2003-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 5455
[patent_no_of_claims] => 20
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[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/873/06873021.pdf
[firstpage_image] =>[orig_patent_app_number] => 10725641
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/725641 | MOS transistors having higher drain current without reduced breakdown voltage | Dec 1, 2003 | Issued |
Array
(
[id] => 700264
[patent_doc_number] => 07067923
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-27
[patent_title] => 'Semiconductor device having hall-effect and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/726392
[patent_app_country] => US
[patent_app_date] => 2003-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 6887
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/067/07067923.pdf
[firstpage_image] =>[orig_patent_app_number] => 10726392
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/726392 | Semiconductor device having hall-effect and manufacturing method thereof | Dec 1, 2003 | Issued |
Array
(
[id] => 7260417
[patent_doc_number] => 20040150104
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-05
[patent_title] => 'Semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/722561
[patent_app_country] => US
[patent_app_date] => 2003-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 8181
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0150/20040150104.pdf
[firstpage_image] =>[orig_patent_app_number] => 10722561
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/722561 | Semiconductor chip with passive element in a wiring region of the chip | Nov 27, 2003 | Issued |
Array
(
[id] => 651253
[patent_doc_number] => 07112830
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-26
[patent_title] => 'Super lattice modification of overlying transistor'
[patent_app_type] => utility
[patent_app_number] => 10/723382
[patent_app_country] => US
[patent_app_date] => 2003-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 20
[patent_no_of_words] => 8278
[patent_no_of_claims] => 30
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/112/07112830.pdf
[firstpage_image] =>[orig_patent_app_number] => 10723382
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/723382 | Super lattice modification of overlying transistor | Nov 24, 2003 | Issued |
Array
(
[id] => 7101433
[patent_doc_number] => 20050104159
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-19
[patent_title] => 'POWER GENERATOR AND METHOD FOR FORMING SAME'
[patent_app_type] => utility
[patent_app_number] => 10/717362
[patent_app_country] => US
[patent_app_date] => 2003-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3488
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0104/20050104159.pdf
[firstpage_image] =>[orig_patent_app_number] => 10717362
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/717362 | Power generator and method for forming same | Nov 18, 2003 | Issued |
Array
(
[id] => 7120346
[patent_doc_number] => 20050012175
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-20
[patent_title] => 'Semiconductor substrate and manufacturing process therefor'
[patent_app_type] => utility
[patent_app_number] => 10/699831
[patent_app_country] => US
[patent_app_date] => 2003-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 9502
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0012/20050012175.pdf
[firstpage_image] =>[orig_patent_app_number] => 10699831
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/699831 | Semiconductor substrate and manufacturing process therefor | Nov 3, 2003 | Abandoned |
Array
(
[id] => 7154385
[patent_doc_number] => 20050082601
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-21
[patent_title] => 'Split gate field effect transistor with a self-aligned control gate'
[patent_app_type] => utility
[patent_app_number] => 10/689462
[patent_app_country] => US
[patent_app_date] => 2003-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0082/20050082601.pdf
[firstpage_image] =>[orig_patent_app_number] => 10689462
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/689462 | Split gate field effect transistor with a self-aligned control gate | Oct 19, 2003 | Abandoned |
Array
(
[id] => 7724665
[patent_doc_number] => 08097937
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-01-17
[patent_title] => 'Leadframe and housing for radiation-emitting component, radiation-emitting component, and a method for producing the component'
[patent_app_type] => utility
[patent_app_number] => 10/683712
[patent_app_country] => US
[patent_app_date] => 2003-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 5816
[patent_no_of_claims] => 33
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[patent_words_short_claim] => 189
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/097/08097937.pdf
[firstpage_image] =>[orig_patent_app_number] => 10683712
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/683712 | Leadframe and housing for radiation-emitting component, radiation-emitting component, and a method for producing the component | Oct 9, 2003 | Issued |
Array
(
[id] => 7154424
[patent_doc_number] => 20050082621
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-21
[patent_title] => 'Substrate-biased I/O and power ESD protection circuits in deep-submicron twin-well process'
[patent_app_type] => utility
[patent_app_number] => 10/676602
[patent_app_country] => US
[patent_app_date] => 2003-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2559
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0082/20050082621.pdf
[firstpage_image] =>[orig_patent_app_number] => 10676602
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/676602 | Substrate-biased I/O and power ESD protection circuits in deep-submicron twin-well process | Sep 30, 2003 | Issued |
Array
(
[id] => 1028484
[patent_doc_number] => 06882052
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-19
[patent_title] => 'Plasma enhanced liner'
[patent_app_type] => utility
[patent_app_number] => 10/665322
[patent_app_country] => US
[patent_app_date] => 2003-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3586
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/882/06882052.pdf
[firstpage_image] =>[orig_patent_app_number] => 10665322
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/665322 | Plasma enhanced liner | Sep 19, 2003 | Issued |
Array
(
[id] => 7205142
[patent_doc_number] => 20040070066
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-15
[patent_title] => 'Power semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/656211
[patent_app_country] => US
[patent_app_date] => 2003-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0070/20040070066.pdf
[firstpage_image] =>[orig_patent_app_number] => 10656211
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/656211 | Power semiconductor device | Sep 7, 2003 | Issued |
Array
(
[id] => 7130209
[patent_doc_number] => 20040041238
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-04
[patent_title] => 'Beta control using a rapid thermal oxidation'
[patent_app_type] => new
[patent_app_number] => 10/653912
[patent_app_country] => US
[patent_app_date] => 2003-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0041/20040041238.pdf
[firstpage_image] =>[orig_patent_app_number] => 10653912
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/653912 | Beta control using a rapid thermal oxidation | Sep 3, 2003 | Issued |
Array
(
[id] => 7445800
[patent_doc_number] => 20040051156
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-18
[patent_title] => 'Method of fabricating a high Q - large tuning range micro-electro mechanical system (MEMS) varactor for broadband applications'
[patent_app_type] => new
[patent_app_number] => 10/654201
[patent_app_country] => US
[patent_app_date] => 2003-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0051/20040051156.pdf
[firstpage_image] =>[orig_patent_app_number] => 10654201
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/654201 | Method of fabricating a high Q - large tuning range micro-electro mechanical system (MEMS) varactor for broadband applications | Sep 2, 2003 | Abandoned |
Array
(
[id] => 6969683
[patent_doc_number] => 20050035393
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-17
[patent_title] => 'SPLIT-GATE NON-VOLATILE MEMORY'
[patent_app_type] => utility
[patent_app_number] => 10/604692
[patent_app_country] => US
[patent_app_date] => 2003-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0035/20050035393.pdf
[firstpage_image] =>[orig_patent_app_number] => 10604692
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/604692 | Split-gate non-volatile memory | Aug 10, 2003 | Issued |
Array
(
[id] => 7030961
[patent_doc_number] => 20050029596
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-10
[patent_title] => 'Method and apparatus for preventing microcircuit thermo-mechanical damage during an ESD event'
[patent_app_type] => utility
[patent_app_number] => 10/635391
[patent_app_country] => US
[patent_app_date] => 2003-08-06
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0029/20050029596.pdf
[firstpage_image] =>[orig_patent_app_number] => 10635391
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/635391 | Method and apparatus for preventing microcircuit thermo-mechanical damage during an ESD event | Aug 5, 2003 | Issued |
Array
(
[id] => 7383188
[patent_doc_number] => 20040029298
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-12
[patent_title] => 'Ferroelectric memory cell and corresponding manufacturing method'
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[patent_app_number] => 10/635063
[patent_app_country] => US
[patent_app_date] => 2003-08-05
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0029/20040029298.pdf
[firstpage_image] =>[orig_patent_app_number] => 10635063
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/635063 | Ferroelectric memory cell and corresponding manufacturing method | Aug 4, 2003 | Abandoned |
Array
(
[id] => 7314377
[patent_doc_number] => 20040222533
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-11
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/628372
[patent_app_country] => US
[patent_app_date] => 2003-07-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0222/20040222533.pdf
[firstpage_image] =>[orig_patent_app_number] => 10628372
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/628372 | Semiconductor device having multi-layer interconnection structure and method of manufacturing the same | Jul 28, 2003 | Issued |
Array
(
[id] => 7415142
[patent_doc_number] => 20040159925
[patent_country] => US
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[patent_title] => 'Semiconductor device and method for manufacture thereof'
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[patent_app_number] => 10/628461
[patent_app_country] => US
[patent_app_date] => 2003-07-29
[patent_effective_date] => 0000-00-00
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0159/20040159925.pdf
[firstpage_image] =>[orig_patent_app_number] => 10628461
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/628461 | Semiconductor device and method for manufacture thereof | Jul 28, 2003 | Abandoned |