Willis Little

Array ( [id] => 1081374 [patent_doc_number] => 06836005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-28 [patent_title] => 'Semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/628462 [patent_app_country] => US [patent_app_date] => 2003-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3263 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/836/06836005.pdf [firstpage_image] =>[orig_patent_app_number] => 10628462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7022943 [patent_doc_number] => 20050017337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Stacking apparatus for integrated circuit assembly' [patent_app_type] => utility [patent_app_number] => 10/622461 [patent_app_country] => US [patent_app_date] => 2003-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1634 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20050017337.pdf [firstpage_image] =>[orig_patent_app_number] => 10622461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6966629 [patent_doc_number] => 20050233526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Semiconductor device, production method and production device thereof' [patent_app_type] => utility [patent_app_number] => 10/521311 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12608 [patent_no_of_claims] => 71 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20050233526.pdf [firstpage_image] =>[orig_patent_app_number] => 10521311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7086594 [patent_doc_number] => 20050006706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Symmetrical high frequency SCR structure and method' [patent_app_type] => utility [patent_app_number] => 10/615171 [patent_app_country] => US [patent_app_date] => 2003-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20050006706.pdf [firstpage_image] =>[orig_patent_app_number] => 10615171 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 487569 [patent_doc_number] => 07218000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Liquid solder thermal interface material contained within a cold-formed barrier and methods of making same' [patent_app_type] => utility [patent_app_number] => 10/607782 [patent_app_country] => US [patent_app_date] => 2003-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 12429 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/218/07218000.pdf [firstpage_image] =>[orig_patent_app_number] => 10607782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7086528 [patent_doc_number] => 20050006640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Polymer-based memory element' [patent_app_type] => utility [patent_app_number] => 10/608791 [patent_app_country] => US [patent_app_date] => 2003-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5936 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20050006640.pdf [firstpage_image] =>[orig_patent_app_number] => 10608791 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7405241 [patent_doc_number] => 20040262762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Method of providing via in a multilayer semiconductor device' [patent_app_type] => new [patent_app_number] => 10/603261 [patent_app_country] => US [patent_app_date] => 2003-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2745 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20040262762.pdf [firstpage_image] =>[orig_patent_app_number] => 10603261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 681059 [patent_doc_number] => 07084456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Trench MOSFET with recessed clamping diode using graded doping' [patent_app_type] => utility [patent_app_number] => 10/606112 [patent_app_country] => US [patent_app_date] => 2003-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 72 [patent_no_of_words] => 17614 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084456.pdf [firstpage_image] =>[orig_patent_app_number] => 10606112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7278823 [patent_doc_number] => 20040061200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Semiconductor wafer and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 10/461352 [patent_app_country] => US [patent_app_date] => 2003-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4731 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20040061200.pdf [firstpage_image] =>[orig_patent_app_number] => 10461352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7220012 [patent_doc_number] => 20040155357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => '[CHIP PACKAGE STRUCTURE AND MANUFACTURING PROCESS THEREOF]' [patent_app_type] => new [patent_app_number] => 10/250186 [patent_app_country] => US [patent_app_date] => 2003-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3228 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20040155357.pdf [firstpage_image] =>[orig_patent_app_number] => 10250186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6723442 [patent_doc_number] => 20030205754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Dynamic electrically alterable programmable read only memory device' [patent_app_type] => new [patent_app_number] => 10/461593 [patent_app_country] => US [patent_app_date] => 2003-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10120 [patent_no_of_claims] => 88 [patent_no_of_ind_claims] => 26 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20030205754.pdf [firstpage_image] =>[orig_patent_app_number] => 10461593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7327577 [patent_doc_number] => 20040253437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Magnetic materials having superparamagnetic particles' [patent_app_type] => new [patent_app_number] => 10/458112 [patent_app_country] => US [patent_app_date] => 2003-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7091 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20040253437.pdf [firstpage_image] =>[orig_patent_app_number] => 10458112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7295762 [patent_doc_number] => 20040124407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Scalable programmable structure, an array including the structure, and methods of forming the same' [patent_app_type] => new [patent_app_number] => 10/458551 [patent_app_country] => US [patent_app_date] => 2003-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12109 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20040124407.pdf [firstpage_image] =>[orig_patent_app_number] => 10458551 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7338645 [patent_doc_number] => 20040245636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'FULL REMOVAL OF DUAL DAMASCENE METAL LEVEL' [patent_app_type] => new [patent_app_number] => 10/250147 [patent_app_country] => US [patent_app_date] => 2003-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2878 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20040245636.pdf [firstpage_image] =>[orig_patent_app_number] => 10250147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 920158 [patent_doc_number] => 07321167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-22 [patent_title] => 'Flex tape architecture for integrated circuit signal ingress/egress' [patent_app_type] => utility [patent_app_number] => 10/455906 [patent_app_country] => US [patent_app_date] => 2003-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 4167 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/321/07321167.pdf [firstpage_image] =>[orig_patent_app_number] => 10455906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9026395 [patent_doc_number] => 08535976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Method for fabricating chip package with die and substrate' [patent_app_type] => utility [patent_app_number] => 10/454972 [patent_app_country] => US [patent_app_date] => 2003-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 41 [patent_no_of_words] => 6933 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10454972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7338611 [patent_doc_number] => 20040245624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Using solder balls of multiple sizes to couple one or more semiconductor structures to an electrical device' [patent_app_type] => new [patent_app_number] => 10/453445 [patent_app_country] => US [patent_app_date] => 2003-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8730 [patent_no_of_claims] => 83 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20040245624.pdf [firstpage_image] =>[orig_patent_app_number] => 10453445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1086553 [patent_doc_number] => 06831365 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-14 [patent_title] => 'Method and pattern for reducing interconnect failures' [patent_app_type] => B1 [patent_app_number] => 10/448656 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2515 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/831/06831365.pdf [firstpage_image] =>[orig_patent_app_number] => 10448656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1128402 [patent_doc_number] => 06791179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Monolithic semiconducting ceramic electronic component' [patent_app_type] => B2 [patent_app_number] => 10/446699 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2971 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/791/06791179.pdf [firstpage_image] =>[orig_patent_app_number] => 10446699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7348319 [patent_doc_number] => 20040012065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/446141 [patent_app_country] => US [patent_app_date] => 2003-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3711 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20040012065.pdf [firstpage_image] =>[orig_patent_app_number] => 10446141 [rel_patent_id] =>[rel_patent_doc_number] =>)