Search

Willis Little

Examiner (ID: 13674)

Most Active Art Unit
3203
Art Unit(s)
2899, 3643, 2107, 2403, 2406, 3203, 3616, 2401, 2103
Total Applications
2327
Issued Applications
2182
Pending Applications
48
Abandoned Applications
97

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16936852 [patent_doc_number] => 20210202741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER [patent_app_type] => utility [patent_app_number] => 17/201728 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17201728 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/201728
Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer Mar 14, 2021 Issued
Array ( [id] => 17463846 [patent_doc_number] => 20220077152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/199740 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199740 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199740
Semiconductor devices having a decreasing height gate structure Mar 11, 2021 Issued
Array ( [id] => 17486111 [patent_doc_number] => 20220093615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/194591 [patent_app_country] => US [patent_app_date] => 2021-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17194591 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/194591
Semiconductor memory device having ferroelectric field effect transistor Mar 7, 2021 Issued
Array ( [id] => 18859171 [patent_doc_number] => 11856781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Three-dimensional memory device and method [patent_app_type] => utility [patent_app_number] => 17/194715 [patent_app_country] => US [patent_app_date] => 2021-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 8828 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17194715 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/194715
Three-dimensional memory device and method Mar 7, 2021 Issued
Array ( [id] => 17431861 [patent_doc_number] => 20220059570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/189197 [patent_app_country] => US [patent_app_date] => 2021-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17189197 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/189197
Ferroelectric-type semiconductor memory device with hole transfer-type layer Feb 28, 2021 Issued
Array ( [id] => 17833744 [patent_doc_number] => 20220271048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => COMMON-CONNECTION METHOD IN 3D MEMORY [patent_app_type] => utility [patent_app_number] => 17/185229 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14478 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185229 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/185229
Common-connection method in 3D memory Feb 24, 2021 Issued
Array ( [id] => 16905121 [patent_doc_number] => 20210184037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => MOS Devices Having Epitaxy Regions with Reduced Facets [patent_app_type] => utility [patent_app_number] => 17/169994 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17169994 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/169994
MOS devices having epitaxy regions with reduced facets Feb 7, 2021 Issued
Array ( [id] => 17303177 [patent_doc_number] => 20210399016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => MEMORY DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/159179 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17159179 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/159179
Memory device comprising conductive pillars and method of forming the same Jan 26, 2021 Issued
Array ( [id] => 17262952 [patent_doc_number] => 20210375937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => MEMORY DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/156645 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17156645 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/156645
Memory device and method of forming the same Jan 24, 2021 Issued
Array ( [id] => 17318997 [patent_doc_number] => 20210408047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/155085 [patent_app_country] => US [patent_app_date] => 2021-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14585 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17155085 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/155085
Three-dimensional memory device and manufacturing method thereof Jan 21, 2021 Issued
Array ( [id] => 17787855 [patent_doc_number] => 11410991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Series resistor over drain region in high voltage device [patent_app_type] => utility [patent_app_number] => 17/155268 [patent_app_country] => US [patent_app_date] => 2021-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 3810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17155268 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/155268
Series resistor over drain region in high voltage device Jan 21, 2021 Issued
Array ( [id] => 17359977 [patent_doc_number] => 20220020773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/151559 [patent_app_country] => US [patent_app_date] => 2021-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11806 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17151559 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/151559
Semiconductor device and manufacturing method of semiconductor device Jan 17, 2021 Issued
Array ( [id] => 17752843 [patent_doc_number] => 20220231048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => THREE-DIMENSIONAL FERROELECTRIC MEMORY DEVICE CONTAINING LATTICE-MATCHED TEMPLATES AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/150561 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150561 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150561
Three-dimensional ferroelectric memory device containing lattice-matched templates and methods of making the same Jan 14, 2021 Issued
Array ( [id] => 18054158 [patent_doc_number] => 11527553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Three-dimensional memory device and method [patent_app_type] => utility [patent_app_number] => 17/140888 [patent_app_country] => US [patent_app_date] => 2021-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 14679 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140888 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/140888
Three-dimensional memory device and method Jan 3, 2021 Issued
Array ( [id] => 19139449 [patent_doc_number] => 11974441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Memory array including epitaxial source lines and bit lines [patent_app_type] => utility [patent_app_number] => 17/138152 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 102 [patent_no_of_words] => 17222 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138152 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/138152
Memory array including epitaxial source lines and bit lines Dec 29, 2020 Issued
Array ( [id] => 18564719 [patent_doc_number] => 11729989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Depletion mode ferroelectric transistors [patent_app_type] => utility [patent_app_number] => 17/137144 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 5619 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137144 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137144
Depletion mode ferroelectric transistors Dec 28, 2020 Issued
Array ( [id] => 17262950 [patent_doc_number] => 20210375935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => Three-Dimensional Memory Device and Method [patent_app_type] => utility [patent_app_number] => 17/133964 [patent_app_country] => US [patent_app_date] => 2020-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133964 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133964
Three-dimensional memory device and method Dec 23, 2020 Issued
Array ( [id] => 18054157 [patent_doc_number] => 11527552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Ferroelectric memory device and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/130609 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 58 [patent_no_of_words] => 13376 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17130609 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/130609
Ferroelectric memory device and method of forming the same Dec 21, 2020 Issued
Array ( [id] => 16752444 [patent_doc_number] => 20210104456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => Electronic Device with Stud Bumps [patent_app_type] => utility [patent_app_number] => 17/127100 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127100 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127100
Electronic device with stud bumps Dec 17, 2020 Issued
Array ( [id] => 16827766 [patent_doc_number] => 20210143059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => HIGH SPEED, HIGH DENSITY, LOW POWER DIE INTERCONNECT SYSTEM [patent_app_type] => utility [patent_app_number] => 17/127021 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19269 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127021 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127021
HIGH SPEED, HIGH DENSITY, LOW POWER DIE INTERCONNECT SYSTEM Dec 17, 2020 Abandoned
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