Search

Willis Little

Examiner (ID: 13674)

Most Active Art Unit
3203
Art Unit(s)
2899, 3643, 2107, 2403, 2406, 3203, 3616, 2401, 2103
Total Applications
2327
Issued Applications
2182
Pending Applications
48
Abandoned Applications
97

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7634390 [patent_doc_number] => 06657230 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Electro-optical device having a symmetrically located contact hole and method of producing the same' [patent_app_type] => B1 [patent_app_number] => 09/600701 [patent_app_country] => US [patent_app_date] => 2000-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 22421 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/657/06657230.pdf [firstpage_image] =>[orig_patent_app_number] => 09600701 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/600701
Electro-optical device having a symmetrically located contact hole and method of producing the same Jul 20, 2000 Issued
Array ( [id] => 7639820 [patent_doc_number] => 06396096 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Design layout for a dense memory cell structure' [patent_app_type] => B1 [patent_app_number] => 09/597401 [patent_app_country] => US [patent_app_date] => 2000-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2699 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396096.pdf [firstpage_image] =>[orig_patent_app_number] => 09597401 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/597401
Design layout for a dense memory cell structure Jun 20, 2000 Issued
Array ( [id] => 1181992 [patent_doc_number] => 06740912 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-25 [patent_title] => 'Semiconductor device free of LLD regions' [patent_app_type] => B1 [patent_app_number] => 09/597012 [patent_app_country] => US [patent_app_date] => 2000-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3632 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/740/06740912.pdf [firstpage_image] =>[orig_patent_app_number] => 09597012 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/597012
Semiconductor device free of LLD regions Jun 19, 2000 Issued
Array ( [id] => 1368382 [patent_doc_number] => 06570210 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Multilayer pillar array capacitor structure for deep sub-micron CMOS' [patent_app_type] => B1 [patent_app_number] => 09/596443 [patent_app_country] => US [patent_app_date] => 2000-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3102 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/570/06570210.pdf [firstpage_image] =>[orig_patent_app_number] => 09596443 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/596443
Multilayer pillar array capacitor structure for deep sub-micron CMOS Jun 18, 2000 Issued
09/595120 Semiconductor trench device with enhanced gate oxide integrity structure Jun 15, 2000 Abandoned
Array ( [id] => 999835 [patent_doc_number] => 06911686 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-28 [patent_title] => 'Semiconductor memory device having planarized upper surface and a SiON moisture barrier' [patent_app_type] => utility [patent_app_number] => 09/594091 [patent_app_country] => US [patent_app_date] => 2000-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 29 [patent_no_of_words] => 9417 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/911/06911686.pdf [firstpage_image] =>[orig_patent_app_number] => 09594091 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/594091
Semiconductor memory device having planarized upper surface and a SiON moisture barrier Jun 14, 2000 Issued
Array ( [id] => 1478842 [patent_doc_number] => 06344669 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'CMOS sensor' [patent_app_type] => B1 [patent_app_number] => 09/593042 [patent_app_country] => US [patent_app_date] => 2000-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 3746 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344669.pdf [firstpage_image] =>[orig_patent_app_number] => 09593042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/593042
CMOS sensor Jun 12, 2000 Issued
Array ( [id] => 1583099 [patent_doc_number] => 06424043 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY MEMORY DEVICES, METHODS OF FORMING CAPACITOR CONTAINERS, METHODS OF MAKING ELECTRICAL CONNECTION TO CIRCUIT NODES AND RELATED INTEGRATED CIRCUITRY' [patent_app_type] => B1 [patent_app_number] => 09/592441 [patent_app_country] => US [patent_app_date] => 2000-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3843 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424043.pdf [firstpage_image] =>[orig_patent_app_number] => 09592441 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/592441
SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY MEMORY DEVICES, METHODS OF FORMING CAPACITOR CONTAINERS, METHODS OF MAKING ELECTRICAL CONNECTION TO CIRCUIT NODES AND RELATED INTEGRATED CIRCUITRY Jun 11, 2000 Issued
Array ( [id] => 1529518 [patent_doc_number] => 06479883 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Electrostatic discharge protection circuit' [patent_app_type] => B1 [patent_app_number] => 09/585563 [patent_app_country] => US [patent_app_date] => 2000-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2582 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479883.pdf [firstpage_image] =>[orig_patent_app_number] => 09585563 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/585563
Electrostatic discharge protection circuit Jun 1, 2000 Issued
09/577201 Integrated IC chip package for electronic image sensor die May 22, 2000 Abandoned
Array ( [id] => 4358904 [patent_doc_number] => 06291860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Self-aligned contacts to source/drain silicon electrodes utilizing polysilicon and silicides' [patent_app_type] => 1 [patent_app_number] => 9/549930 [patent_app_country] => US [patent_app_date] => 2000-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 3107 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291860.pdf [firstpage_image] =>[orig_patent_app_number] => 549930 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/549930
Self-aligned contacts to source/drain silicon electrodes utilizing polysilicon and silicides Apr 13, 2000 Issued
Array ( [id] => 4282298 [patent_doc_number] => 06281538 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Multi-layer tunneling device with a graded stoichiometry insulating layer' [patent_app_type] => 1 [patent_app_number] => 9/532572 [patent_app_country] => US [patent_app_date] => 2000-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3786 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281538.pdf [firstpage_image] =>[orig_patent_app_number] => 532572 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/532572
Multi-layer tunneling device with a graded stoichiometry insulating layer Mar 21, 2000 Issued
Array ( [id] => 4388191 [patent_doc_number] => 06278167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Semiconductor sensor with a base element and at least one deformation element' [patent_app_type] => 1 [patent_app_number] => 9/531203 [patent_app_country] => US [patent_app_date] => 2000-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3491 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278167.pdf [firstpage_image] =>[orig_patent_app_number] => 531203 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531203
Semiconductor sensor with a base element and at least one deformation element Mar 19, 2000 Issued
Array ( [id] => 1436591 [patent_doc_number] => 06355962 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'CMOS FET with P-well with P- type halo under drain and counterdoped N- halo under source region' [patent_app_type] => B1 [patent_app_number] => 09/524520 [patent_app_country] => US [patent_app_date] => 2000-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4075 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355962.pdf [firstpage_image] =>[orig_patent_app_number] => 09524520 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/524520
CMOS FET with P-well with P- type halo under drain and counterdoped N- halo under source region Mar 12, 2000 Issued
Array ( [id] => 1182228 [patent_doc_number] => 06740962 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-25 [patent_title] => 'Tape stiffener, semiconductor device component assemblies including same, and stereolithographic methods for fabricating same' [patent_app_type] => B1 [patent_app_number] => 09/512203 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 8956 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/740/06740962.pdf [firstpage_image] =>[orig_patent_app_number] => 09512203 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/512203
Tape stiffener, semiconductor device component assemblies including same, and stereolithographic methods for fabricating same Feb 23, 2000 Issued
Array ( [id] => 4401333 [patent_doc_number] => 06297535 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection' [patent_app_type] => 1 [patent_app_number] => 9/510096 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 4360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297535.pdf [firstpage_image] =>[orig_patent_app_number] => 510096 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510096
Transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection Feb 21, 2000 Issued
Array ( [id] => 1490111 [patent_doc_number] => 06402009 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Apparatus and method for shaping lead frame for semiconductor device and lead frame for semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/504852 [patent_app_country] => US [patent_app_date] => 2000-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 4451 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/402/06402009.pdf [firstpage_image] =>[orig_patent_app_number] => 09504852 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/504852
Apparatus and method for shaping lead frame for semiconductor device and lead frame for semiconductor device Feb 15, 2000 Issued
Array ( [id] => 1441058 [patent_doc_number] => 06495914 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Multi-chip module structure having conductive blocks to provide electrical connection between conductors on first and second sides of a conductive base substrate' [patent_app_type] => B1 [patent_app_number] => 09/485400 [patent_app_country] => US [patent_app_date] => 2000-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 32 [patent_no_of_words] => 5611 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495914.pdf [firstpage_image] =>[orig_patent_app_number] => 09485400 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/485400
Multi-chip module structure having conductive blocks to provide electrical connection between conductors on first and second sides of a conductive base substrate Feb 9, 2000 Issued
Array ( [id] => 1497061 [patent_doc_number] => 06404027 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'High dielectric constant gate oxides for silicon-based devices' [patent_app_type] => B1 [patent_app_number] => 09/499411 [patent_app_country] => US [patent_app_date] => 2000-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2980 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404027.pdf [firstpage_image] =>[orig_patent_app_number] => 09499411 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/499411
High dielectric constant gate oxides for silicon-based devices Feb 6, 2000 Issued
Array ( [id] => 1351609 [patent_doc_number] => 06580108 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Insulated gate bipolar transistor decreasing the gate resistance' [patent_app_type] => B1 [patent_app_number] => 09/497213 [patent_app_country] => US [patent_app_date] => 2000-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2253 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/580/06580108.pdf [firstpage_image] =>[orig_patent_app_number] => 09497213 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/497213
Insulated gate bipolar transistor decreasing the gate resistance Feb 2, 2000 Issued
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