Application number | Title of the application | Filing Date | Status |
---|
Array
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[id] => 1428126
[patent_doc_number] => 06504212
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-07
[patent_title] => 'Method and apparatus for enhanced SOI passgate operations'
[patent_app_type] => B1
[patent_app_number] => 09/497361
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[patent_app_date] => 2000-02-03
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Array
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[patent_doc_number] => 06404060
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-11
[patent_title] => 'Semiconductor device having a chip-on-chip structure'
[patent_app_type] => B1
[patent_app_number] => 09/496191
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[patent_app_date] => 2000-02-02
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09/487083 | Silicon On Insulator Circuit Structure With Buried Semiconductor Interconnect Structure And Method For Forming Same | Jan 18, 2000 | Abandoned |
Array
(
[id] => 6415512
[patent_doc_number] => 20020125568
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-09-12
[patent_title] => 'Method Of Fabricating Chip-Scale Packages And Resulting Structures'
[patent_app_type] => new
[patent_app_number] => 09/483712
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[patent_app_date] => 2000-01-14
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/483712 | Method Of Fabricating Chip-Scale Packages And Resulting Structures | Jan 13, 2000 | Abandoned |
09/482101 | ORGANIC FLIP CHIP PACKAGES WITH AN ARRAY OF THROUGH HOLE PINS | Jan 12, 2000 | Abandoned |
Array
(
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[patent_doc_number] => 06762474
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[patent_kind] => B1
[patent_issue_date] => 2004-07-13
[patent_title] => 'Method and apparatus for temperature compensation of read-only memory'
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Array
(
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[patent_doc_number] => 06353267
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[patent_issue_date] => 2002-03-05
[patent_title] => 'Semiconductor device having first and second sealing resins'
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[patent_app_date] => 2000-01-05
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Array
(
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[patent_kind] => B1
[patent_issue_date] => 2006-03-28
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[patent_app_type] => utility
[patent_app_number] => 09/476961
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Array
(
[id] => 1120956
[patent_doc_number] => 06798076
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-28
[patent_title] => 'Method and apparatus for encoding information in an IC package'
[patent_app_type] => B2
[patent_app_number] => 09/470092
[patent_app_country] => US
[patent_app_date] => 1999-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/798/06798076.pdf
[firstpage_image] =>[orig_patent_app_number] => 09470092
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/470092 | Method and apparatus for encoding information in an IC package | Dec 20, 1999 | Issued |
09/454003 | DEFINE VIA IN DUAL DAMASCENE PROCESS | Dec 2, 1999 | Abandoned |
Array
(
[id] => 4331447
[patent_doc_number] => 06329678
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-11
[patent_title] => 'Semiconductor memory array'
[patent_app_type] => 1
[patent_app_number] => 9/451852
[patent_app_country] => US
[patent_app_date] => 1999-12-01
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 451852
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/451852 | Semiconductor memory array | Nov 30, 1999 | Issued |
Array
(
[id] => 1552814
[patent_doc_number] => 06399974
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-04
[patent_title] => 'Semiconductor memory device using an insulator film for the capacitor of the memory cell and method for manufacturing the same'
[patent_app_type] => B1
[patent_app_number] => 09/441823
[patent_app_country] => US
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Array
(
[id] => 1410776
[patent_doc_number] => 06534861
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-18
[patent_title] => 'Ball grid substrate for lead-on-chip semiconductor package'
[patent_app_type] => B1
[patent_app_number] => 09/440630
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/440630 | Ball grid substrate for lead-on-chip semiconductor package | Nov 14, 1999 | Issued |
Array
(
[id] => 4333740
[patent_doc_number] => 06320243
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'Defect removable semiconductor devices and manufacturing methods thereof'
[patent_app_type] => 1
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[pdf_file] => patents/06/320/06320243.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/434623 | Defect removable semiconductor devices and manufacturing methods thereof | Nov 4, 1999 | Issued |
Array
(
[id] => 1246715
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[patent_kind] => B1
[patent_issue_date] => 2004-01-13
[patent_title] => 'Semiconductor device having steady substrate potential'
[patent_app_type] => B1
[patent_app_number] => 09/433382
[patent_app_country] => US
[patent_app_date] => 1999-11-03
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09/433591 | METHOD AND SYSTEM FOR REDUCING ARC LAYER REMOVAL DURING REMOVAL OF PHOTORESIST | Nov 1, 1999 | Abandoned |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/431593 | Semiconductor device having an integral resistance element | Oct 31, 1999 | Issued |
Array
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Array
(
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[patent_kind] => NA
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Array
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