Search

Willis Little

Examiner (ID: 13674)

Most Active Art Unit
3203
Art Unit(s)
2899, 3643, 2107, 2403, 2406, 3203, 3616, 2401, 2103
Total Applications
2327
Issued Applications
2182
Pending Applications
48
Abandoned Applications
97

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 491649 [patent_doc_number] => 07215029 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-08 [patent_title] => 'Multilayer interconnection structure of a semiconductor' [patent_app_type] => utility [patent_app_number] => 09/225351 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4284 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/215/07215029.pdf [firstpage_image] =>[orig_patent_app_number] => 09225351 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225351
Multilayer interconnection structure of a semiconductor Jan 4, 1999 Issued
09/225403 CONTACT-BUMPLESS CHIP CONTACTING METHOD AND AN ELECTRONIC CIRCUIT PRODUCED BY SAID METHOD Jan 4, 1999 Abandoned
Array ( [id] => 4210098 [patent_doc_number] => 06078088 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Low dielectric semiconductor device with rigid lined interconnection system' [patent_app_type] => 1 [patent_app_number] => 9/225541 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2828 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078088.pdf [firstpage_image] =>[orig_patent_app_number] => 225541 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225541
Low dielectric semiconductor device with rigid lined interconnection system Jan 4, 1999 Issued
Array ( [id] => 5948509 [patent_doc_number] => 20020005533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-17 [patent_title] => 'SUBSTRATE PLATE TRENCH DRAM CELL WITH LIGHTLY DOPED SUBSTRATE' [patent_app_type] => new [patent_app_number] => 09/222652 [patent_app_country] => US [patent_app_date] => 1998-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3558 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20020005533.pdf [firstpage_image] =>[orig_patent_app_number] => 09222652 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/222652
SUBSTRATE PLATE TRENCH DRAM CELL WITH LIGHTLY DOPED SUBSTRATE Dec 29, 1998 Abandoned
Array ( [id] => 4360505 [patent_doc_number] => 06218697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Contact in semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/221972 [patent_app_country] => US [patent_app_date] => 1998-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1875 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218697.pdf [firstpage_image] =>[orig_patent_app_number] => 221972 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/221972
Contact in semiconductor memory device Dec 28, 1998 Issued
Array ( [id] => 4414288 [patent_doc_number] => 06229189 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Multi-function optoelectronic device structure' [patent_app_type] => 1 [patent_app_number] => 9/222612 [patent_app_country] => US [patent_app_date] => 1998-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 2451 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229189.pdf [firstpage_image] =>[orig_patent_app_number] => 222612 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/222612
Multi-function optoelectronic device structure Dec 23, 1998 Issued
Array ( [id] => 4361263 [patent_doc_number] => 06201291 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Semiconductor device and method of manufacturing such a device' [patent_app_type] => 1 [patent_app_number] => 9/209063 [patent_app_country] => US [patent_app_date] => 1998-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3121 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/201/06201291.pdf [firstpage_image] =>[orig_patent_app_number] => 209063 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/209063
Semiconductor device and method of manufacturing such a device Dec 9, 1998 Issued
09/208082 METHOD AND SYSTEM FOR AVOIDING PLASMA ETCH DAMAGE Dec 8, 1998 Abandoned
Array ( [id] => 999856 [patent_doc_number] => 06911707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-28 [patent_title] => 'Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance' [patent_app_type] => utility [patent_app_number] => 09/207972 [patent_app_country] => US [patent_app_date] => 1998-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 6229 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/911/06911707.pdf [firstpage_image] =>[orig_patent_app_number] => 09207972 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/207972
Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance Dec 8, 1998 Issued
Array ( [id] => 4176968 [patent_doc_number] => 06140706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Semiconductor device and method of manufacturing without damaging HSQ layer and metal pattern utilizing multiple dielectric layers' [patent_app_type] => 1 [patent_app_number] => 9/206951 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1971 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140706.pdf [firstpage_image] =>[orig_patent_app_number] => 206951 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/206951
Semiconductor device and method of manufacturing without damaging HSQ layer and metal pattern utilizing multiple dielectric layers Dec 7, 1998 Issued
Array ( [id] => 4385658 [patent_doc_number] => 06303974 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Semiconductor chips encapsulated within a preformed sub-assembly' [patent_app_type] => 1 [patent_app_number] => 9/206673 [patent_app_country] => US [patent_app_date] => 1998-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2939 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303974.pdf [firstpage_image] =>[orig_patent_app_number] => 206673 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/206673
Semiconductor chips encapsulated within a preformed sub-assembly Dec 6, 1998 Issued
Array ( [id] => 4090831 [patent_doc_number] => 06025633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Multi-level transistor fabrication method having an inverted, upper level transistor which shares a gate conductor with a non-inverted, lower level transistor' [patent_app_type] => 1 [patent_app_number] => 9/203773 [patent_app_country] => US [patent_app_date] => 1998-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4177 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025633.pdf [firstpage_image] =>[orig_patent_app_number] => 203773 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/203773
Multi-level transistor fabrication method having an inverted, upper level transistor which shares a gate conductor with a non-inverted, lower level transistor Dec 1, 1998 Issued
Array ( [id] => 4361293 [patent_doc_number] => 06201293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Electro optical devices with reduced filter thinning on the edge pixel photosites and method of producing same' [patent_app_type] => 1 [patent_app_number] => 9/196462 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5381 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/201/06201293.pdf [firstpage_image] =>[orig_patent_app_number] => 196462 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196462
Electro optical devices with reduced filter thinning on the edge pixel photosites and method of producing same Nov 18, 1998 Issued
Array ( [id] => 4389788 [patent_doc_number] => 06262456 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Integrated circuit having transistors with different threshold voltages' [patent_app_type] => 1 [patent_app_number] => 9/187842 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 4980 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/262/06262456.pdf [firstpage_image] =>[orig_patent_app_number] => 187842 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187842
Integrated circuit having transistors with different threshold voltages Nov 5, 1998 Issued
Array ( [id] => 4161565 [patent_doc_number] => 06104069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Semiconductor device having an elevated active region formed in an oxide trench' [patent_app_type] => 1 [patent_app_number] => 9/187462 [patent_app_country] => US [patent_app_date] => 1998-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 2968 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104069.pdf [firstpage_image] =>[orig_patent_app_number] => 187462 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187462
Semiconductor device having an elevated active region formed in an oxide trench Nov 3, 1998 Issued
Array ( [id] => 1448071 [patent_doc_number] => 06369427 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Integrated circuitry, interface circuit of an integrated circuit device, and cascode circuitry' [patent_app_type] => B1 [patent_app_number] => 09/185411 [patent_app_country] => US [patent_app_date] => 1998-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/369/06369427.pdf [firstpage_image] =>[orig_patent_app_number] => 09185411 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/185411
Integrated circuitry, interface circuit of an integrated circuit device, and cascode circuitry Nov 2, 1998 Issued
Array ( [id] => 4413878 [patent_doc_number] => 06300678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'I/O pin having solder dam for connecting substrates' [patent_app_type] => 1 [patent_app_number] => 9/184081 [patent_app_country] => US [patent_app_date] => 1998-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 42 [patent_no_of_words] => 6723 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300678.pdf [firstpage_image] =>[orig_patent_app_number] => 184081 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/184081
I/O pin having solder dam for connecting substrates Nov 1, 1998 Issued
Array ( [id] => 1257323 [patent_doc_number] => 06667537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-23 [patent_title] => 'Semiconductor devices including resistance elements and fuse elements' [patent_app_type] => B1 [patent_app_number] => 09/178873 [patent_app_country] => US [patent_app_date] => 1998-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 29 [patent_no_of_words] => 7762 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/667/06667537.pdf [firstpage_image] =>[orig_patent_app_number] => 09178873 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/178873
Semiconductor devices including resistance elements and fuse elements Oct 25, 1998 Issued
09/176192 SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING AN ELECTRODE PAD PORTION FROM BEING PEELED OFF Oct 20, 1998 Abandoned
Array ( [id] => 4179862 [patent_doc_number] => 06084280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Transistor having a metal silicide self-aligned to the gate' [patent_app_type] => 1 [patent_app_number] => 9/173233 [patent_app_country] => US [patent_app_date] => 1998-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 4798 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/084/06084280.pdf [firstpage_image] =>[orig_patent_app_number] => 173233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/173233
Transistor having a metal silicide self-aligned to the gate Oct 14, 1998 Issued
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