Application number | Title of the application | Filing Date | Status |
---|
Array
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[patent_doc_number] => 07215029
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[patent_issue_date] => 2007-05-08
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09/225403 | CONTACT-BUMPLESS CHIP CONTACTING METHOD AND AN ELECTRONIC CIRCUIT PRODUCED BY SAID METHOD | Jan 4, 1999 | Abandoned |
Array
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[patent_issue_date] => 2000-06-20
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Array
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[patent_doc_number] => 20020005533
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[patent_issue_date] => 2002-01-17
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[patent_app_type] => new
[patent_app_number] => 09/222652
[patent_app_country] => US
[patent_app_date] => 1998-12-30
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Array
(
[id] => 4360505
[patent_doc_number] => 06218697
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-17
[patent_title] => 'Contact in semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 9/221972
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[patent_app_date] => 1998-12-29
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[firstpage_image] =>[orig_patent_app_number] => 221972
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Array
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[patent_kind] => NA
[patent_issue_date] => 2001-05-08
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[firstpage_image] =>[orig_patent_app_number] => 222612
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Array
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[id] => 4361263
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-13
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09/208082 | METHOD AND SYSTEM FOR AVOIDING PLASMA ETCH DAMAGE | Dec 8, 1998 | Abandoned |
Array
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[patent_kind] => B2
[patent_issue_date] => 2005-06-28
[patent_title] => 'Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance'
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[patent_app_number] => 09/207972
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Array
(
[id] => 4176968
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[patent_issue_date] => 2000-10-31
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[patent_app_type] => 1
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Array
(
[id] => 4385658
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[patent_title] => 'Semiconductor chips encapsulated within a preformed sub-assembly'
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Array
(
[id] => 4090831
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[patent_kind] => NA
[patent_issue_date] => 2000-02-15
[patent_title] => 'Multi-level transistor fabrication method having an inverted, upper level transistor which shares a gate conductor with a non-inverted, lower level transistor'
[patent_app_type] => 1
[patent_app_number] => 9/203773
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Array
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[id] => 4361293
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[patent_issue_date] => 2001-03-13
[patent_title] => 'Electro optical devices with reduced filter thinning on the edge pixel photosites and method of producing same'
[patent_app_type] => 1
[patent_app_number] => 9/196462
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/196462 | Electro optical devices with reduced filter thinning on the edge pixel photosites and method of producing same | Nov 18, 1998 | Issued |
Array
(
[id] => 4389788
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Array
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[id] => 4161565
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[patent_kind] => NA
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Array
(
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[patent_kind] => B1
[patent_issue_date] => 2002-04-09
[patent_title] => 'Integrated circuitry, interface circuit of an integrated circuit device, and cascode circuitry'
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Array
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[patent_title] => 'I/O pin having solder dam for connecting substrates'
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[firstpage_image] =>[orig_patent_app_number] => 184081
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Array
(
[id] => 1257323
[patent_doc_number] => 06667537
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-23
[patent_title] => 'Semiconductor devices including resistance elements and fuse elements'
[patent_app_type] => B1
[patent_app_number] => 09/178873
[patent_app_country] => US
[patent_app_date] => 1998-10-26
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/178873 | Semiconductor devices including resistance elements and fuse elements | Oct 25, 1998 | Issued |
09/176192 | SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING AN ELECTRODE PAD PORTION FROM BEING PEELED OFF | Oct 20, 1998 | Abandoned |
Array
(
[id] => 4179862
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[patent_kind] => NA
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/173233 | Transistor having a metal silicide self-aligned to the gate | Oct 14, 1998 | Issued |