Search

Willis Little

Examiner (ID: 13674)

Most Active Art Unit
3203
Art Unit(s)
2899, 3643, 2107, 2403, 2406, 3203, 3616, 2401, 2103
Total Applications
2327
Issued Applications
2182
Pending Applications
48
Abandoned Applications
97

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4108740 [patent_doc_number] => 06051884 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Method of forming interconnections in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/118291 [patent_app_country] => US [patent_app_date] => 1998-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2549 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051884.pdf [firstpage_image] =>[orig_patent_app_number] => 118291 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/118291
Method of forming interconnections in an integrated circuit Jul 16, 1998 Issued
Array ( [id] => 3980934 [patent_doc_number] => 05917244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Integrated circuit inductor structure formed employing copper containing conductor winding layer clad with nickel containing conductor layer' [patent_app_type] => 1 [patent_app_number] => 9/119022 [patent_app_country] => US [patent_app_date] => 1998-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7378 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917244.pdf [firstpage_image] =>[orig_patent_app_number] => 119022 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/119022
Integrated circuit inductor structure formed employing copper containing conductor winding layer clad with nickel containing conductor layer Jul 16, 1998 Issued
09/116343 SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME Jul 15, 1998 Abandoned
Array ( [id] => 4108287 [patent_doc_number] => 06100561 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation' [patent_app_type] => 1 [patent_app_number] => 9/115332 [patent_app_country] => US [patent_app_date] => 1998-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 53 [patent_no_of_words] => 13861 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100561.pdf [firstpage_image] =>[orig_patent_app_number] => 115332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/115332
Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation Jul 13, 1998 Issued
Array ( [id] => 4180097 [patent_doc_number] => 06084296 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Low cost high power hermetic package with electrical feed-through bushings' [patent_app_type] => 1 [patent_app_number] => 9/112683 [patent_app_country] => US [patent_app_date] => 1998-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4769 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/084/06084296.pdf [firstpage_image] =>[orig_patent_app_number] => 112683 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/112683
Low cost high power hermetic package with electrical feed-through bushings Jul 8, 1998 Issued
Array ( [id] => 4365907 [patent_doc_number] => 06255677 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Chip-based analysis device comprising electrodes with localized heating' [patent_app_type] => 1 [patent_app_number] => 9/111773 [patent_app_country] => US [patent_app_date] => 1998-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4838 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255677.pdf [firstpage_image] =>[orig_patent_app_number] => 111773 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/111773
Chip-based analysis device comprising electrodes with localized heating Jul 7, 1998 Issued
Array ( [id] => 1411041 [patent_doc_number] => 06534878 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Optimizing the power connection between chip and circuit board for a power switch' [patent_app_type] => B1 [patent_app_number] => 09/101371 [patent_app_country] => US [patent_app_date] => 1998-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 975 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/534/06534878.pdf [firstpage_image] =>[orig_patent_app_number] => 09101371 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/101371
Optimizing the power connection between chip and circuit board for a power switch Jul 7, 1998 Issued
Array ( [id] => 7026643 [patent_doc_number] => 20010013629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'MULTI-LAYER GATE DIELECTRIC' [patent_app_type] => new [patent_app_number] => 09/109261 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2028 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20010013629.pdf [firstpage_image] =>[orig_patent_app_number] => 09109261 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/109261
MULTI-LAYER GATE DIELECTRIC Jun 29, 1998 Abandoned
Array ( [id] => 4422753 [patent_doc_number] => 06194782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Mechanically-stabilized area-array device package' [patent_app_type] => 1 [patent_app_number] => 9/103802 [patent_app_country] => US [patent_app_date] => 1998-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4576 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194782.pdf [firstpage_image] =>[orig_patent_app_number] => 103802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/103802
Mechanically-stabilized area-array device package Jun 23, 1998 Issued
Array ( [id] => 4412968 [patent_doc_number] => 06239478 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Semiconductor structure for a MOS transistor' [patent_app_type] => 1 [patent_app_number] => 9/095263 [patent_app_country] => US [patent_app_date] => 1998-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2475 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239478.pdf [firstpage_image] =>[orig_patent_app_number] => 095263 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/095263
Semiconductor structure for a MOS transistor Jun 9, 1998 Issued
09/095231 NON-LINEAR, SILICON RESISTIVE ELEMENT FOR SEMICONDUCTOR DEVICES Jun 9, 1998 Abandoned
Array ( [id] => 4091099 [patent_doc_number] => 06025651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Semiconductor package structures using epoxy molding compound pads and a method for fabricating the epoxy molding compound pads' [patent_app_type] => 1 [patent_app_number] => 9/090861 [patent_app_country] => US [patent_app_date] => 1998-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3007 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025651.pdf [firstpage_image] =>[orig_patent_app_number] => 090861 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/090861
Semiconductor package structures using epoxy molding compound pads and a method for fabricating the epoxy molding compound pads Jun 4, 1998 Issued
Array ( [id] => 4162932 [patent_doc_number] => 06114719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Magnetic tunnel junction memory cell with in-stack biasing of the free ferromagnetic layer and memory array using the cell' [patent_app_type] => 1 [patent_app_number] => 9/087553 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9133 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114719.pdf [firstpage_image] =>[orig_patent_app_number] => 087553 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/087553
Magnetic tunnel junction memory cell with in-stack biasing of the free ferromagnetic layer and memory array using the cell May 28, 1998 Issued
Array ( [id] => 4410720 [patent_doc_number] => 06232628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Semiconductor device having stacked capacitor structure' [patent_app_type] => 1 [patent_app_number] => 9/086752 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5621 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232628.pdf [firstpage_image] =>[orig_patent_app_number] => 086752 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086752
Semiconductor device having stacked capacitor structure May 28, 1998 Issued
Array ( [id] => 3984877 [patent_doc_number] => 05949112 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Integrated circuits with tub-ties' [patent_app_type] => 1 [patent_app_number] => 9/085913 [patent_app_country] => US [patent_app_date] => 1998-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4841 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949112.pdf [firstpage_image] =>[orig_patent_app_number] => 085913 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/085913
Integrated circuits with tub-ties May 27, 1998 Issued
Array ( [id] => 4094610 [patent_doc_number] => 06133598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Semiconductor device with diagonal capacitor bit line and fabrication method thereof' [patent_app_type] => 1 [patent_app_number] => 9/084982 [patent_app_country] => US [patent_app_date] => 1998-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3818 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133598.pdf [firstpage_image] =>[orig_patent_app_number] => 084982 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/084982
Semiconductor device with diagonal capacitor bit line and fabrication method thereof May 27, 1998 Issued
Array ( [id] => 4113290 [patent_doc_number] => 06057577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Component of protection of an integrated MOS power transistor against voltage gradients' [patent_app_type] => 1 [patent_app_number] => 9/085521 [patent_app_country] => US [patent_app_date] => 1998-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1927 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057577.pdf [firstpage_image] =>[orig_patent_app_number] => 085521 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/085521
Component of protection of an integrated MOS power transistor against voltage gradients May 26, 1998 Issued
Array ( [id] => 6444579 [patent_doc_number] => 20020149062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-17 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 09/081613 [patent_app_country] => US [patent_app_date] => 1998-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 24784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20020149062.pdf [firstpage_image] =>[orig_patent_app_number] => 09081613 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/081613
Semiconductor device May 19, 1998 Issued
Array ( [id] => 4309871 [patent_doc_number] => 06252257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Isolating wall between power components' [patent_app_type] => 1 [patent_app_number] => 9/081051 [patent_app_country] => US [patent_app_date] => 1998-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3148 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252257.pdf [firstpage_image] =>[orig_patent_app_number] => 081051 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/081051
Isolating wall between power components May 18, 1998 Issued
Array ( [id] => 4413896 [patent_doc_number] => 06300680 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Semiconductor substrate and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 9/073762 [patent_app_country] => US [patent_app_date] => 1998-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 6240 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300680.pdf [firstpage_image] =>[orig_patent_app_number] => 073762 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/073762
Semiconductor substrate and manufacturing method thereof May 6, 1998 Issued
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