Willis Little

Array ( [id] => 1597191 [patent_doc_number] => 06384478 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Leadframe having a paddle with an isolated area' [patent_app_type] => B1 [patent_app_number] => 09/073779 [patent_app_country] => US [patent_app_date] => 1998-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3047 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/384/06384478.pdf [firstpage_image] =>[orig_patent_app_number] => 09073779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4140503 [patent_doc_number] => 06015987 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Semiconductor device having capacitor exhibiting improved mositure resistance and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 9/071122 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 7099 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/015/06015987.pdf [firstpage_image] =>[orig_patent_app_number] => 071122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4101744 [patent_doc_number] => 06097071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'ESD protection clamp for mixed voltage I/O stages using NMOS transistors' [patent_app_type] => 1 [patent_app_number] => 9/072130 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4373 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097071.pdf [firstpage_image] =>[orig_patent_app_number] => 072130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4301279 [patent_doc_number] => 06184572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Interlevel dielectric stack containing plasma deposited fluorinated amorphous carbon films for semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/069723 [patent_app_country] => US [patent_app_date] => 1998-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3957 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184572.pdf [firstpage_image] =>[orig_patent_app_number] => 069723 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1427822 [patent_doc_number] => 06504175 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Hybrid polycrystalline and amorphous silicon structures on a shared substrate' [patent_app_type] => B1 [patent_app_number] => 09/067943 [patent_app_country] => US [patent_app_date] => 1998-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4973 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504175.pdf [firstpage_image] =>[orig_patent_app_number] => 09067943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4423645 [patent_doc_number] => 06177710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Semiconductor waveguide type photodetector and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/011620 [patent_app_country] => US [patent_app_date] => 1998-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 8419 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177710.pdf [firstpage_image] =>[orig_patent_app_number] => 011620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4389746 [patent_doc_number] => 06262453 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Double gate-oxide for reducing gate-drain capacitance in trenched DMOS with high-dopant concentration buried-region under trenched gate' [patent_app_type] => 1 [patent_app_number] => 9/066033 [patent_app_country] => US [patent_app_date] => 1998-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 5181 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/262/06262453.pdf [firstpage_image] =>[orig_patent_app_number] => 066033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4105094 [patent_doc_number] => 06066876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Integrated circuit arrangement having at least one MOS transistor manufactured by use of a planar transistor layout' [patent_app_type] => 1 [patent_app_number] => 9/065173 [patent_app_country] => US [patent_app_date] => 1998-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3366 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066876.pdf [firstpage_image] =>[orig_patent_app_number] => 065173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4297562 [patent_doc_number] => 06236098 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Heat spreader' [patent_app_type] => 1 [patent_app_number] => 9/061452 [patent_app_country] => US [patent_app_date] => 1998-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 7568 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236098.pdf [firstpage_image] =>[orig_patent_app_number] => 061452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4111321 [patent_doc_number] => 06023083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Semiconductor device having a conductor pattern side face provided with a separate conductive sidewall' [patent_app_type] => 1 [patent_app_number] => 9/061060 [patent_app_country] => US [patent_app_date] => 1998-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 6342 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023083.pdf [firstpage_image] =>[orig_patent_app_number] => 061060 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4137500 [patent_doc_number] => 06147378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Fully recessed semiconductor device and method for low power applications with single wrap around buried drain region' [patent_app_type] => 1 [patent_app_number] => 9/052060 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 5633 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147378.pdf [firstpage_image] =>[orig_patent_app_number] => 052060 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4137486 [patent_doc_number] => 06147377 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Fully recessed semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/052061 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 5041 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147377.pdf [firstpage_image] =>[orig_patent_app_number] => 052061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6985553 [patent_doc_number] => 20010035544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => new [patent_app_number] => 09/050113 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 24215 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20010035544.pdf [firstpage_image] =>[orig_patent_app_number] => 09050113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309503 [patent_doc_number] => 06188104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Trench DMOS device having an amorphous silicon and polysilicon gate' [patent_app_type] => 1 [patent_app_number] => 9/049601 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2971 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188104.pdf [firstpage_image] =>[orig_patent_app_number] => 049601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4293870 [patent_doc_number] => 06211537 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'LED array' [patent_app_type] => 1 [patent_app_number] => 9/040450 [patent_app_country] => US [patent_app_date] => 1998-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 4545 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211537.pdf [firstpage_image] =>[orig_patent_app_number] => 040450 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4187190 [patent_doc_number] => 06020622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Trench isolation for semiconductor device with lateral projections above substrate' [patent_app_type] => 1 [patent_app_number] => 9/038111 [patent_app_country] => US [patent_app_date] => 1998-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 3263 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020622.pdf [firstpage_image] =>[orig_patent_app_number] => 038111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4163031 [patent_doc_number] => 06114726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Low voltage MOSFET' [patent_app_type] => 1 [patent_app_number] => 9/038453 [patent_app_country] => US [patent_app_date] => 1998-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2101 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114726.pdf [firstpage_image] =>[orig_patent_app_number] => 038453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4196354 [patent_doc_number] => 06130459 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Over-voltage protection device for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/037771 [patent_app_country] => US [patent_app_date] => 1998-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3747 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130459.pdf [firstpage_image] =>[orig_patent_app_number] => 037771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4294180 [patent_doc_number] => 06211559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Symmetric magnetic tunnel device' [patent_app_type] => 1 [patent_app_number] => 9/032107 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3364 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211559.pdf [firstpage_image] =>[orig_patent_app_number] => 032107 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4190590 [patent_doc_number] => 06160297 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Semiconductor memory device having a first source line arranged between a memory cell string and bit lines in the direction crossing the bit lines and a second source line arranged in parallel to the bit lines' [patent_app_type] => 1 [patent_app_number] => 9/017803 [patent_app_country] => US [patent_app_date] => 1998-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 128 [patent_no_of_words] => 11984 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/160/06160297.pdf [firstpage_image] =>[orig_patent_app_number] => 017803 [rel_patent_id] =>[rel_patent_doc_number] =>)