
Wilner Jean Baptiste
Examiner (ID: 6775, Phone: (571)270-7394 , Office: P/2823 )
| Most Active Art Unit | 2899 |
| Art Unit(s) | 2823, 2899 |
| Total Applications | 1318 |
| Issued Applications | 1104 |
| Pending Applications | 82 |
| Abandoned Applications | 156 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20411401
[patent_doc_number] => 20250380511
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-11
[patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE INCLUDING POWER DISTRIBUTION GRIDS
[patent_app_type] => utility
[patent_app_number] => 19/232184
[patent_app_country] => US
[patent_app_date] => 2025-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 49286
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19232184
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/232184 | 3D semiconductor device and structure including power distribution grids | Jun 8, 2025 | Issued |
Array
(
[id] => 20002376
[patent_doc_number] => 20250140598
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-01
[patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE INCLUDING POWER DISTRIBUTION GRIDS
[patent_app_type] => utility
[patent_app_number] => 19/004133
[patent_app_country] => US
[patent_app_date] => 2024-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 49071
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19004133
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/004133 | 3D semiconductor device and structure including power distribution grids | Dec 26, 2024 | Issued |
Array
(
[id] => 19560023
[patent_doc_number] => 20240371815
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-07
[patent_title] => PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/774943
[patent_app_country] => US
[patent_app_date] => 2024-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6579
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774943
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/774943 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF | Jul 16, 2024 | Pending |
Array
(
[id] => 20305408
[patent_doc_number] => 12451408
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-21
[patent_title] => Package structures
[patent_app_type] => utility
[patent_app_number] => 18/772247
[patent_app_country] => US
[patent_app_date] => 2024-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 2048
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772247
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/772247 | Package structures | Jul 13, 2024 | Issued |
Array
(
[id] => 19546630
[patent_doc_number] => 20240363666
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-31
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS
[patent_app_type] => utility
[patent_app_number] => 18/771052
[patent_app_country] => US
[patent_app_date] => 2024-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12372
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771052
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/771052 | Semiconductor device and method of manufacturing the same, and electronic apparatus | Jul 11, 2024 | Issued |
Array
(
[id] => 19484042
[patent_doc_number] => 20240332084
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => METHODS OF REDUCING PARASITIC CAPACITANCE IN SEMICONDUTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/738707
[patent_app_country] => US
[patent_app_date] => 2024-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8372
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738707
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/738707 | Methods of reducing parasitic capacitance in semicondutor devices | Jun 9, 2024 | Issued |
Array
(
[id] => 20111608
[patent_doc_number] => 12362344
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-15
[patent_title] => Semiconductor package and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 18/736766
[patent_app_country] => US
[patent_app_date] => 2024-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 9252
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18736766
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/736766 | Semiconductor package and method of manufacturing the same | Jun 6, 2024 | Issued |
Array
(
[id] => 19436151
[patent_doc_number] => 20240304649
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-12
[patent_title] => SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS
[patent_app_type] => utility
[patent_app_number] => 18/668941
[patent_app_country] => US
[patent_app_date] => 2024-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 82231
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 305
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668941
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/668941 | Solid-state imaging device and electronic apparatus | May 19, 2024 | Issued |
Array
(
[id] => 19393023
[patent_doc_number] => 20240282893
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-22
[patent_title] => DISPLAY PANEL, DISPLAY DEVICE, AND METHOD FOR PREPARING DISPLAY PANEL
[patent_app_type] => utility
[patent_app_number] => 18/651101
[patent_app_country] => US
[patent_app_date] => 2024-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10441
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18651101
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/651101 | DISPLAY PANEL, DISPLAY DEVICE, AND METHOD FOR PREPARING DISPLAY PANEL | Apr 29, 2024 | Pending |
Array
(
[id] => 19384683
[patent_doc_number] => 20240274553
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-15
[patent_title] => INTERPOSER, METHOD FOR FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE HAVING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/643474
[patent_app_country] => US
[patent_app_date] => 2024-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14990
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643474
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/643474 | Interposer, method for fabricating the same, and semiconductor package having the same | Apr 22, 2024 | Issued |
Array
(
[id] => 20139531
[patent_doc_number] => 20250246575
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-31
[patent_title] => Apparatus and Bonding Process for Wafer Bonding
[patent_app_type] => utility
[patent_app_number] => 18/641927
[patent_app_country] => US
[patent_app_date] => 2024-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2251
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641927
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/641927 | Apparatus and Bonding Process for Wafer Bonding | Apr 21, 2024 | Pending |
Array
(
[id] => 19964945
[patent_doc_number] => 12334465
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-17
[patent_title] => Semiconductor package and method of forming same
[patent_app_type] => utility
[patent_app_number] => 18/631900
[patent_app_country] => US
[patent_app_date] => 2024-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 3361
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631900
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/631900 | Semiconductor package and method of forming same | Apr 9, 2024 | Issued |
Array
(
[id] => 20292931
[patent_doc_number] => 20250318174
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-09
[patent_title] => TRANSISTOR CONTACT STRUCTURE WITH UPPER LEVEL INSULATING SPACER AND METHOD OF MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/628059
[patent_app_country] => US
[patent_app_date] => 2024-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5840
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18628059
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/628059 | TRANSISTOR CONTACT STRUCTURE WITH UPPER LEVEL INSULATING SPACER AND METHOD OF MAKING THE SAME | Apr 4, 2024 | Pending |
Array
(
[id] => 19741403
[patent_doc_number] => 12218251
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-04
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 18/626594
[patent_app_country] => US
[patent_app_date] => 2024-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 53
[patent_no_of_words] => 23871
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626594
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/626594 | Semiconductor device | Apr 3, 2024 | Issued |
Array
(
[id] => 20292868
[patent_doc_number] => 20250318111
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-09
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/625431
[patent_app_country] => US
[patent_app_date] => 2024-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625431
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/625431 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | Apr 2, 2024 | Pending |
Array
(
[id] => 19335514
[patent_doc_number] => 20240249944
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-25
[patent_title] => REDUCE WELL DOPANT LOSS IN FINFETS THROUGH CO-IMPLANTATION
[patent_app_type] => utility
[patent_app_number] => 18/625651
[patent_app_country] => US
[patent_app_date] => 2024-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7609
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625651
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/625651 | REDUCE WELL DOPANT LOSS IN FINFETS THROUGH CO-IMPLANTATION | Apr 2, 2024 | Pending |
Array
(
[id] => 19305888
[patent_doc_number] => 20240234468
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-11
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS
[patent_app_type] => utility
[patent_app_number] => 18/615151
[patent_app_country] => US
[patent_app_date] => 2024-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12357
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615151
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/615151 | Semiconductor device and method of manufacturing the same, and electronic apparatus | Mar 24, 2024 | Issued |
Array
(
[id] => 20900415
[patent_doc_number] => 12707695
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-08-11
[patent_title] => Semiconductor device and method for forming the same
[patent_app_type] => utility
[patent_app_number] => 18/613149
[patent_app_country] => US
[patent_app_date] => 2024-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 15
[patent_no_of_words] => 0
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18613149
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/613149 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME | Mar 21, 2024 | Pending |
Array
(
[id] => 19305798
[patent_doc_number] => 20240234378
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-11
[patent_title] => SEMICONDUCTOR ASSEMBLIES WITH SYSTEM AND METHODS FOR ALIGNING DIES USING REGISTRATION MARKS
[patent_app_type] => utility
[patent_app_number] => 18/614583
[patent_app_country] => US
[patent_app_date] => 2024-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5706
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614583
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/614583 | SEMICONDUCTOR ASSEMBLIES WITH SYSTEM AND METHODS FOR ALIGNING DIES USING REGISTRATION MARKS | Mar 21, 2024 | Pending |
Array
(
[id] => 19901521
[patent_doc_number] => 12279474
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-15
[patent_title] => OLED panel lower part protection film, and organic light-emitting display apparatus comprising same
[patent_app_type] => utility
[patent_app_number] => 18/614499
[patent_app_country] => US
[patent_app_date] => 2024-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 6557
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614499
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/614499 | OLED panel lower part protection film, and organic light-emitting display apparatus comprising same | Mar 21, 2024 | Issued |