Search

Wilner Jean Baptiste

Examiner (ID: 2332, Phone: (571)270-7394 , Office: P/2823 )

Most Active Art Unit
2899
Art Unit(s)
2899, 2823
Total Applications
1296
Issued Applications
1084
Pending Applications
84
Abandoned Applications
155

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17949370 [patent_doc_number] => 20220336389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => SEMICONDUCTOR DEVICE WITH BARRIER LAYER AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/234282 [patent_app_country] => US [patent_app_date] => 2021-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17234282 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/234282
Semiconductor device with barrier layer and method for fabricating the same Apr 18, 2021 Issued
Array ( [id] => 18371899 [patent_doc_number] => 11652081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Method for manufacturing semiconductor package structure [patent_app_type] => utility [patent_app_number] => 17/233245 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8151 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17233245 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/233245
Method for manufacturing semiconductor package structure Apr 15, 2021 Issued
Array ( [id] => 17318892 [patent_doc_number] => 20210407942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => Packaged Semiconductor Device and Method of Forming Thereof [patent_app_type] => utility [patent_app_number] => 17/232528 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17986 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232528 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232528
Packaged semiconductor device and method of forming thereof Apr 15, 2021 Issued
Array ( [id] => 17018350 [patent_doc_number] => 11087995 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-10 [patent_title] => 3D semiconductor device and structure [patent_app_type] => utility [patent_app_number] => 17/222960 [patent_app_country] => US [patent_app_date] => 2021-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 75 [patent_no_of_words] => 49689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222960 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/222960
3D semiconductor device and structure Apr 4, 2021 Issued
Array ( [id] => 18735716 [patent_doc_number] => 11804457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Package structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/219905 [patent_app_country] => US [patent_app_date] => 2021-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 37 [patent_no_of_words] => 13477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219905 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219905
Package structure and manufacturing method thereof Mar 31, 2021 Issued
Array ( [id] => 17917635 [patent_doc_number] => 20220320031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => GLASS-BASED BONDING STRUCTURES FOR POWER ELECTRONICS [patent_app_type] => utility [patent_app_number] => 17/219133 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4908 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219133 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219133
Glass-based bonding structures for power electronics Mar 30, 2021 Issued
Array ( [id] => 17448369 [patent_doc_number] => 20220068874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE AND APPARATUS FOR PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/218581 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17218581 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/218581
Method of manufacturing a semiconductor package and apparatus for performing the same Mar 30, 2021 Issued
Array ( [id] => 18759901 [patent_doc_number] => 11810941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => 3D image sensor [patent_app_type] => utility [patent_app_number] => 17/217167 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 8053 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17217167 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/217167
3D image sensor Mar 29, 2021 Issued
Array ( [id] => 17900809 [patent_doc_number] => 20220310471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => INTEGRATED CIRCUIT DIE STACKED WITH BACKER DIE INCLUDING CAPACITORS AND THERMAL VIAS [patent_app_type] => utility [patent_app_number] => 17/213974 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4181 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213974 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213974
Integrated circuit die stacked with backer die including capacitors and thermal vias Mar 25, 2021 Issued
Array ( [id] => 16951713 [patent_doc_number] => 20210210405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => CHIP PACKAGE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/211104 [patent_app_country] => US [patent_app_date] => 2021-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211104 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/211104
Chip package and electronic device Mar 23, 2021 Issued
Array ( [id] => 16993183 [patent_doc_number] => 20210231603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => DIFFERENTIAL SENSING WITH BIOFET SENSORS [patent_app_type] => utility [patent_app_number] => 17/208596 [patent_app_country] => US [patent_app_date] => 2021-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17208596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/208596
Differential sensing with BioFET sensors Mar 21, 2021 Issued
Array ( [id] => 18563022 [patent_doc_number] => 11728275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Semiconductor package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/206117 [patent_app_country] => US [patent_app_date] => 2021-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 8366 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17206117 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/206117
Semiconductor package and manufacturing method thereof Mar 17, 2021 Issued
Array ( [id] => 17277965 [patent_doc_number] => 20210384163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => POWER MODULE [patent_app_type] => utility [patent_app_number] => 17/203938 [patent_app_country] => US [patent_app_date] => 2021-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17203938 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/203938
Power module Mar 16, 2021 Issued
Array ( [id] => 17130340 [patent_doc_number] => 20210305109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => Module with Gas Flow-Inhibiting Sealing at Module Interface to Mounting Base [patent_app_type] => utility [patent_app_number] => 17/201239 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7441 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17201239 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/201239
Module with gas flow-inhibiting sealing at module interface to mounting base Mar 14, 2021 Issued
Array ( [id] => 17855255 [patent_doc_number] => 20220285298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => HYBRID POCKET POST AND TAILORED VIA DIELECTRIC FOR 3D-INTEGRATED ELECTRICAL DEVICE [patent_app_type] => utility [patent_app_number] => 17/190850 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7087 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17190850 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/190850
Hybrid pocket post and tailored via dielectric for 3D-integrated electrical device Mar 2, 2021 Issued
Array ( [id] => 18528720 [patent_doc_number] => 11715723 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Wafer on wafer bonding structure [patent_app_type] => utility [patent_app_number] => 17/186984 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 46 [patent_no_of_words] => 11304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17186984 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/186984
Wafer on wafer bonding structure Feb 25, 2021 Issued
Array ( [id] => 16904889 [patent_doc_number] => 20210183805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => BACK SIDE METALLIZATION [patent_app_type] => utility [patent_app_number] => 17/185605 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185605 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/185605
Back side metallization Feb 24, 2021 Issued
Array ( [id] => 18906074 [patent_doc_number] => 20240021559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => FIRST CHIP AND WAFER BONDING METHOD AND CHIP STACKING STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/252490 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18252490 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/252490
FIRST CHIP AND WAFER BONDING METHOD AND CHIP STACKING STRUCTURE Feb 24, 2021 Pending
Array ( [id] => 17810880 [patent_doc_number] => 20220262715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => METHOD AND APPARATUS FOR THROUGH SILICON DIE LEVEL INTERCONNECT [patent_app_type] => utility [patent_app_number] => 17/178971 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6158 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17178971 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/178971
Method and apparatus for through silicon die level interconnect Feb 17, 2021 Issued
Array ( [id] => 18704651 [patent_doc_number] => 11791168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Method for creating a wettable surface for improved reliability in QFN packages [patent_app_type] => utility [patent_app_number] => 17/172043 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6114 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17172043 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/172043
Method for creating a wettable surface for improved reliability in QFN packages Feb 8, 2021 Issued
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