
Wilner Jean Baptiste
Examiner (ID: 2332, Phone: (571)270-7394 , Office: P/2823 )
| Most Active Art Unit | 2899 |
| Art Unit(s) | 2899, 2823 |
| Total Applications | 1296 |
| Issued Applications | 1084 |
| Pending Applications | 84 |
| Abandoned Applications | 155 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19116560
[patent_doc_number] => 20240128310
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-18
[patent_title] => SEMICONDUCTOR DEVICE HAVING SUPPORTER PATTERN
[patent_app_type] => utility
[patent_app_number] => 18/396302
[patent_app_country] => US
[patent_app_date] => 2023-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7259
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18396302
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/396302 | Semiconductor device having supporter pattern | Dec 25, 2023 | Issued |
Array
(
[id] => 20074259
[patent_doc_number] => 20250212481
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-26
[patent_title] => FORKSHEET DEVICE ARCHITECTURE IN STANDARD CELLS
[patent_app_type] => utility
[patent_app_number] => 18/390959
[patent_app_country] => US
[patent_app_date] => 2023-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6175
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -28
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18390959
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/390959 | FORKSHEET DEVICE ARCHITECTURE IN STANDARD CELLS | Dec 19, 2023 | Pending |
Array
(
[id] => 19323385
[patent_doc_number] => 20240244933
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/390159
[patent_app_country] => US
[patent_app_date] => 2023-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21955
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18390159
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/390159 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME | Dec 19, 2023 | Pending |
Array
(
[id] => 19101073
[patent_doc_number] => 20240120301
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-11
[patent_title] => INTEGRATED CIRCUIT CHIP INCLUDING A PASSIVATION NITRIDE LAYER IN CONTACT WITH A HIGH VOLTAGE BONDING PAD AND METHOD OF MAKING
[patent_app_type] => utility
[patent_app_number] => 18/544747
[patent_app_country] => US
[patent_app_date] => 2023-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2787
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18544747
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/544747 | Integrated circuit chip including a passivation nitride layer in contact with a high voltage bonding pad and method of making | Dec 18, 2023 | Issued |
Array
(
[id] => 19054992
[patent_doc_number] => 20240096961
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => Source/Drain Metal Contact and Formation Thereof
[patent_app_type] => utility
[patent_app_number] => 18/520996
[patent_app_country] => US
[patent_app_date] => 2023-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9035
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18520996
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/520996 | Source/drain metal contact and formation thereof | Nov 27, 2023 | Issued |
Array
(
[id] => 19206425
[patent_doc_number] => 20240178324
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-30
[patent_title] => CRYSTALLINE INZNO OXIDE SEMICONDUCTOR, METHOD OF FORMING THE SAME, AND SEMICONDUCTOR DEVICE INCLUDING THE CRYSTALLINE INZNO OXIDE SEMICONDUCTOR
[patent_app_type] => utility
[patent_app_number] => 18/518735
[patent_app_country] => US
[patent_app_date] => 2023-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4676
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518735
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/518735 | CRYSTALLINE INZNO OXIDE SEMICONDUCTOR, METHOD OF FORMING THE SAME, AND SEMICONDUCTOR DEVICE INCLUDING THE CRYSTALLINE INZNO OXIDE SEMICONDUCTOR | Nov 23, 2023 | Pending |
Array
(
[id] => 19054750
[patent_doc_number] => 20240096719
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/516969
[patent_app_country] => US
[patent_app_date] => 2023-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8010
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18516969
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/516969 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | Nov 21, 2023 | Pending |
Array
(
[id] => 19189668
[patent_doc_number] => 20240168581
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-23
[patent_title] => DISPLAY APPARATUS
[patent_app_type] => utility
[patent_app_number] => 18/514851
[patent_app_country] => US
[patent_app_date] => 2023-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15735
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18514851
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/514851 | DISPLAY APPARATUS | Nov 19, 2023 | Pending |
Array
(
[id] => 19951350
[patent_doc_number] => 12322721
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-03
[patent_title] => Asymmetric Stackup Structure for SoC package substrates
[patent_app_type] => utility
[patent_app_number] => 18/513167
[patent_app_country] => US
[patent_app_date] => 2023-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 4252
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513167
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/513167 | Asymmetric Stackup Structure for SoC package substrates | Nov 16, 2023 | Issued |
Array
(
[id] => 19239481
[patent_doc_number] => 20240196677
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-13
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/510659
[patent_app_country] => US
[patent_app_date] => 2023-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16738
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18510659
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/510659 | DISPLAY DEVICE | Nov 15, 2023 | Pending |
Array
(
[id] => 19054679
[patent_doc_number] => 20240096648
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => Seal Ring Designs Supporting Efficient Die to Die Routing
[patent_app_type] => utility
[patent_app_number] => 18/509801
[patent_app_country] => US
[patent_app_date] => 2023-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11036
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 40
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18509801
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/509801 | Seal ring designs supporting efficient die to die routing | Nov 14, 2023 | Issued |
Array
(
[id] => 19038260
[patent_doc_number] => 20240088075
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-14
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/508807
[patent_app_country] => US
[patent_app_date] => 2023-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11725
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18508807
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/508807 | Semiconductor package | Nov 13, 2023 | Issued |
Array
(
[id] => 19351394
[patent_doc_number] => 20240260358
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/501558
[patent_app_country] => US
[patent_app_date] => 2023-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7539
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18501558
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/501558 | DISPLAY DEVICE | Nov 2, 2023 | Pending |
Array
(
[id] => 19494322
[patent_doc_number] => 12113046
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-08
[patent_title] => Method for preparing semiconductor device with wire bond
[patent_app_type] => utility
[patent_app_number] => 18/386345
[patent_app_country] => US
[patent_app_date] => 2023-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 6708
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18386345
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/386345 | Method for preparing semiconductor device with wire bond | Nov 1, 2023 | Issued |
Array
(
[id] => 19998214
[patent_doc_number] => 20250136436
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-01
[patent_title] => MEMS SWITCH WITH PLANAR THROUGH GLASS VIAS (TGV)
[patent_app_type] => utility
[patent_app_number] => 18/498766
[patent_app_country] => US
[patent_app_date] => 2023-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18498766
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/498766 | MEMS SWITCH WITH PLANAR THROUGH GLASS VIAS (TGV) | Oct 30, 2023 | Pending |
Array
(
[id] => 20132325
[patent_doc_number] => 12374643
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-29
[patent_title] => Die with metal pillars
[patent_app_type] => utility
[patent_app_number] => 18/497691
[patent_app_country] => US
[patent_app_date] => 2023-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18497691
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/497691 | Die with metal pillars | Oct 29, 2023 | Issued |
Array
(
[id] => 18958899
[patent_doc_number] => 20240047226
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-08
[patent_title] => METHOD FOR CREATING A WETTABLE SURFACE FOR IMPROVED RELIABILITY IN QFN PACKAGES
[patent_app_type] => utility
[patent_app_number] => 18/488990
[patent_app_country] => US
[patent_app_date] => 2023-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6134
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18488990
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/488990 | Method for creating a wettable surface for improved reliability in QFN packages | Oct 16, 2023 | Issued |
Array
(
[id] => 18943560
[patent_doc_number] => 20240038699
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-01
[patent_title] => SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/380404
[patent_app_country] => US
[patent_app_date] => 2023-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12273
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18380404
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/380404 | Semiconductor chip and semiconductor package including the same | Oct 15, 2023 | Issued |
Array
(
[id] => 20346065
[patent_doc_number] => 12469800
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-11
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 18/485291
[patent_app_country] => US
[patent_app_date] => 2023-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18485291
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/485291 | Semiconductor device | Oct 10, 2023 | Issued |
Array
(
[id] => 19539460
[patent_doc_number] => 12132017
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-29
[patent_title] => Method of soldering a semiconductor chip to a chip carrier
[patent_app_type] => utility
[patent_app_number] => 18/483977
[patent_app_country] => US
[patent_app_date] => 2023-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 5161
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18483977
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/483977 | Method of soldering a semiconductor chip to a chip carrier | Oct 9, 2023 | Issued |