Search

Wilner Jean Baptiste

Examiner (ID: 6775, Phone: (571)270-7394 , Office: P/2823 )

Most Active Art Unit
2899
Art Unit(s)
2823, 2899
Total Applications
1318
Issued Applications
1104
Pending Applications
82
Abandoned Applications
156

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19943695 [patent_doc_number] => 12315831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Package structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/474234 [patent_app_country] => US [patent_app_date] => 2023-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 37 [patent_no_of_words] => 7925 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18474234 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/474234
Package structure and manufacturing method thereof Sep 25, 2023 Issued
Array ( [id] => 19071278 [patent_doc_number] => 20240105704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => 3D Package with Chip-on-Reconstituted Wafer or Reconstituted Wafer-on-Reconstituted Wafer Bonding [patent_app_type] => utility [patent_app_number] => 18/458918 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18458918 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/458918
3D Package with Chip-on-Reconstituted Wafer or Reconstituted Wafer-on-Reconstituted Wafer Bonding Aug 29, 2023 Pending
Array ( [id] => 20853290 [patent_doc_number] => 12690344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-21 [patent_title] => Display device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 18/238550 [patent_app_country] => US [patent_app_date] => 2023-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11963 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18238550 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/238550
DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME Aug 27, 2023 Issued
Array ( [id] => 19010143 [patent_doc_number] => 20240074214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/455937 [patent_app_country] => US [patent_app_date] => 2023-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35976 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18455937 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/455937
SEMICONDUCTOR MEMORY DEVICE Aug 24, 2023 Pending
Array ( [id] => 20692135 [patent_doc_number] => 12622311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Method for assembling EIC to PIC to build an optical engine [patent_app_type] => utility [patent_app_number] => 18/449253 [patent_app_country] => US [patent_app_date] => 2023-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5129 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18449253 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/449253
Method for assembling EIC to PIC to build an optical engine Aug 13, 2023 Issued
Array ( [id] => 19943701 [patent_doc_number] => 12315837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Storage layers for wafer bonding [patent_app_type] => utility [patent_app_number] => 18/447968 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2125 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447968 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447968
Storage layers for wafer bonding Aug 9, 2023 Issued
Array ( [id] => 20162998 [patent_doc_number] => 12389655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Circuit devices with gate seals [patent_app_type] => utility [patent_app_number] => 18/447467 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 1131 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447467 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447467
Circuit devices with gate seals Aug 9, 2023 Issued
Array ( [id] => 19349312 [patent_doc_number] => 20240258276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SEMICONDUCTOR PACKAGES AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/446844 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446844 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446844
SEMICONDUCTOR PACKAGES AND METHOD FOR FABRICATING THE SAME Aug 8, 2023 Pending
Array ( [id] => 19980311 [patent_doc_number] => 12347799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Bond pad structure coupled to multiple interconnect conductive\ structures through trench in substrate [patent_app_type] => utility [patent_app_number] => 18/366844 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 4058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366844 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/366844
Bond pad structure coupled to multiple interconnect conductive structures through trench in substrate Aug 7, 2023 Issued
Array ( [id] => 18789470 [patent_doc_number] => 20230378140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => METHOD OF FABRICATING SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/363731 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12657 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363731 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/363731
Method of fabricating semiconductor package Jul 31, 2023 Issued
Array ( [id] => 18812553 [patent_doc_number] => 20230386890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE INCLUDING POWER DISTRIBUTION GRIDS [patent_app_type] => utility [patent_app_number] => 18/228907 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 53971 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228907 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/228907
3D semiconductor device and structure including power distribution grids Jul 31, 2023 Issued
Array ( [id] => 19741164 [patent_doc_number] => 12218009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Semiconductor package and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/363458 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 8894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363458 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/363458
Semiconductor package and methods of forming the same Jul 31, 2023 Issued
Array ( [id] => 20754803 [patent_doc_number] => 20260157036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-06-04 [patent_title] => DISPLAY SUBSTRATE AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/697409 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18697409 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/697409
DISPLAY SUBSTRATE AND DISPLAY DEVICE Jul 30, 2023 Pending
Array ( [id] => 19926299 [patent_doc_number] => 12300593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Semiconductor device and method of manufacture [patent_app_type] => utility [patent_app_number] => 18/360169 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360169 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360169
Semiconductor device and method of manufacture Jul 26, 2023 Issued
Array ( [id] => 20612911 [patent_doc_number] => 12588533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Grain structure engineering for metal gapfill materials [patent_app_type] => utility [patent_app_number] => 18/225286 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18225286 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/225286
Grain structure engineering for metal gapfill materials Jul 23, 2023 Issued
Array ( [id] => 20118397 [patent_doc_number] => 12368115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Supporting InFO packages to reduce warpage [patent_app_type] => utility [patent_app_number] => 18/357421 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 2190 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357421 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357421
Supporting InFO packages to reduce warpage Jul 23, 2023 Issued
Array ( [id] => 18757579 [patent_doc_number] => 20230361042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => Partial Barrier Free Vias for Cobalt-Based Interconnects and Methods of Fabrication Thereof [patent_app_type] => utility [patent_app_number] => 18/357500 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11765 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357500 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357500
Partial barrier free vias for cobalt-based interconnects and methods of fabrication thereof Jul 23, 2023 Issued
Array ( [id] => 18905984 [patent_doc_number] => 20240021469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => Protection Structures for Bonded Wafers [patent_app_type] => utility [patent_app_number] => 18/356843 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356843 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356843
Protection structures for bonded wafers Jul 20, 2023 Issued
Array ( [id] => 18943556 [patent_doc_number] => 20240038695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => VIA FORMED IN A WAFER USING A FRONT-SIDE AND A BACK-SIDE PROCESS [patent_app_type] => utility [patent_app_number] => 18/217898 [patent_app_country] => US [patent_app_date] => 2023-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18217898 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/217898
VIA FORMED IN A WAFER USING A FRONT-SIDE AND A BACK-SIDE PROCESS Jul 2, 2023 Issued
Array ( [id] => 19926245 [patent_doc_number] => 12300538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Fin field effect transistor (FinFET) device structure with protection layer and method for forming the same [patent_app_type] => utility [patent_app_number] => 18/346573 [patent_app_country] => US [patent_app_date] => 2023-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 3284 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346573 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/346573
Fin field effect transistor (FinFET) device structure with protection layer and method for forming the same Jul 2, 2023 Issued
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