
Wilner Jean Baptiste
Examiner (ID: 6775, Phone: (571)270-7394 , Office: P/2823 )
| Most Active Art Unit | 2899 |
| Art Unit(s) | 2823, 2899 |
| Total Applications | 1318 |
| Issued Applications | 1104 |
| Pending Applications | 82 |
| Abandoned Applications | 156 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20509310
[patent_doc_number] => 12543604
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-02-03
[patent_title] => Adding sealing material to wafer edge for wafer bonding
[patent_app_type] => utility
[patent_app_number] => 18/151663
[patent_app_country] => US
[patent_app_date] => 2023-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 2067
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151663
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/151663 | Adding sealing material to wafer edge for wafer bonding | Jan 8, 2023 | Issued |
Array
(
[id] => 18361037
[patent_doc_number] => 20230142628
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-11
[patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE INCLUDING POWER DISTRIBUTION GRIDS
[patent_app_type] => utility
[patent_app_number] => 18/092253
[patent_app_country] => US
[patent_app_date] => 2022-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 53253
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092253
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/092253 | 3D semiconductor device and structure including power distribution grids | Dec 30, 2022 | Issued |
Array
(
[id] => 19286043
[patent_doc_number] => 20240222521
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-04
[patent_title] => TECHNOLOGIES FOR RIBBON FIELD EFFECT TRANSISTORS WITH VARIABLE FIN NUMBERS
[patent_app_type] => utility
[patent_app_number] => 18/091676
[patent_app_country] => US
[patent_app_date] => 2022-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14675
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091676
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/091676 | TECHNOLOGIES FOR RIBBON FIELD EFFECT TRANSISTORS WITH VARIABLE FIN NUMBERS | Dec 29, 2022 | Pending |
Array
(
[id] => 20705930
[patent_doc_number] => 12628662
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-05-12
[patent_title] => Semiconductor chip, chip system, method of forming a semiconductor chip, and method of forming a chip system
[patent_app_type] => utility
[patent_app_number] => 18/085746
[patent_app_country] => US
[patent_app_date] => 2022-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 1176
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18085746
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/085746 | Semiconductor chip, chip system, method of forming a semiconductor chip, and method of forming a chip system | Dec 20, 2022 | Issued |
Array
(
[id] => 19444486
[patent_doc_number] => 12094775
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-17
[patent_title] => Nanoscale-aligned three-dimensional stacked integrated circuit
[patent_app_type] => utility
[patent_app_number] => 18/081047
[patent_app_country] => US
[patent_app_date] => 2022-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 33
[patent_no_of_words] => 6571
[patent_no_of_claims] => 65
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18081047
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/081047 | Nanoscale-aligned three-dimensional stacked integrated circuit | Dec 13, 2022 | Issued |
Array
(
[id] => 18299216
[patent_doc_number] => 20230108902
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-06
[patent_title] => SELECTIVE UNDERFILL ASSEMBLY AND METHOD THEREFOR
[patent_app_type] => utility
[patent_app_number] => 18/064641
[patent_app_country] => US
[patent_app_date] => 2022-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4120
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064641
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/064641 | Selective underfill assembly and method therefor | Dec 11, 2022 | Issued |
Array
(
[id] => 19639627
[patent_doc_number] => 12170242
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-17
[patent_title] => Fan-out wafer level package structure
[patent_app_type] => utility
[patent_app_number] => 18/064624
[patent_app_country] => US
[patent_app_date] => 2022-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3444
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064624
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/064624 | Fan-out wafer level package structure | Dec 11, 2022 | Issued |
Array
(
[id] => 18943555
[patent_doc_number] => 20240038694
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-01
[patent_title] => THROUGH-SUBSTRATE VIA FORMED USING A PARTIAL PLUG THAT STOPS BEFORE A SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 18/076210
[patent_app_country] => US
[patent_app_date] => 2022-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11121
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18076210
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/076210 | Via formed using a partial plug that stops before a substrate | Dec 5, 2022 | Issued |
Array
(
[id] => 19221525
[patent_doc_number] => 20240186229
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-06
[patent_title] => INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP LAYERS COMPRISING SPIN-ON GLASS (SOG)
[patent_app_type] => utility
[patent_app_number] => 18/061283
[patent_app_country] => US
[patent_app_date] => 2022-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14331
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18061283
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/061283 | INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP LAYERS COMPRISING SPIN-ON GLASS (SOG) | Dec 1, 2022 | Pending |
Array
(
[id] => 19414862
[patent_doc_number] => 12080699
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-03
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 18/054172
[patent_app_country] => US
[patent_app_date] => 2022-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 8838
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18054172
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/054172 | Semiconductor device | Nov 9, 2022 | Issued |
Array
(
[id] => 18379806
[patent_doc_number] => 20230154895
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-18
[patent_title] => PIXEL DEVICE FOR LED DISPLAY AND LED DISPLAY APPARATUS HAVING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/982524
[patent_app_country] => US
[patent_app_date] => 2022-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17702
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17982524
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/982524 | Pixel device for LED display and led display apparatus having the same | Nov 7, 2022 | Issued |
Array
(
[id] => 19101078
[patent_doc_number] => 20240120306
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-11
[patent_title] => SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/980571
[patent_app_country] => US
[patent_app_date] => 2022-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4124
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17980571
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/980571 | Semiconductor package and fabrication method thereof | Nov 3, 2022 | Issued |
Array
(
[id] => 18209258
[patent_doc_number] => 20230055518
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-23
[patent_title] => Solder Ball Application for Singular Die
[patent_app_type] => utility
[patent_app_number] => 18/048513
[patent_app_country] => US
[patent_app_date] => 2022-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6700
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18048513
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/048513 | Solder ball application for singular die | Oct 20, 2022 | Issued |
Array
(
[id] => 18198676
[patent_doc_number] => 20230052195
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-16
[patent_title] => INTERPOSER, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF FABRICATING THE INTERPOSER
[patent_app_type] => utility
[patent_app_number] => 17/971321
[patent_app_country] => US
[patent_app_date] => 2022-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9956
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17971321
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/971321 | Interposer, semiconductor package including the same, and method of fabricating the interposer | Oct 20, 2022 | Issued |
Array
(
[id] => 20626158
[patent_doc_number] => 12593688
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-03-31
[patent_title] => Manufacturing method of diamond composite wafer
[patent_app_type] => utility
[patent_app_number] => 17/970964
[patent_app_country] => US
[patent_app_date] => 2022-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 58
[patent_no_of_words] => 6226
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17970964
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/970964 | Manufacturing method of diamond composite wafer | Oct 20, 2022 | Issued |
Array
(
[id] => 18848949
[patent_doc_number] => 20230411353
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-21
[patent_title] => DIODE AND BIPOLAR JUNCTION TRANSISTOR FOR 3D SFET WITH BSPDN STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/969402
[patent_app_country] => US
[patent_app_date] => 2022-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5669
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17969402
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/969402 | Diode and bipolar junction transistor for 3D SFET with BSPDN structure | Oct 18, 2022 | Issued |
Array
(
[id] => 19116406
[patent_doc_number] => 20240128156
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-18
[patent_title] => Microfluidic Channels for Cooling Hybrid Bonded Interfaces
[patent_app_type] => utility
[patent_app_number] => 17/966486
[patent_app_country] => US
[patent_app_date] => 2022-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7174
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17966486
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/966486 | Microfluidic Channels for Cooling Hybrid Bonded Interfaces | Oct 13, 2022 | Pending |
Array
(
[id] => 20318145
[patent_doc_number] => 12456700
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-28
[patent_title] => Semiconductor die having an optical detection marker and method of producing the semiconductor die
[patent_app_type] => utility
[patent_app_number] => 17/962131
[patent_app_country] => US
[patent_app_date] => 2022-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 1226
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17962131
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/962131 | Semiconductor die having an optical detection marker and method of producing the semiconductor die | Oct 6, 2022 | Issued |
Array
(
[id] => 18312420
[patent_doc_number] => 20230116320
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-13
[patent_title] => Stacked Integrated Circuit Device
[patent_app_type] => utility
[patent_app_number] => 17/938135
[patent_app_country] => US
[patent_app_date] => 2022-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20236
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -31
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17938135
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/938135 | Stacked integrated circuit device | Oct 4, 2022 | Issued |
Array
(
[id] => 19886941
[patent_doc_number] => 12272673
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-08
[patent_title] => Capacitive coupling in a direct-bonded interface for microelectronic devices
[patent_app_type] => utility
[patent_app_number] => 17/959585
[patent_app_country] => US
[patent_app_date] => 2022-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5434
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17959585
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/959585 | Capacitive coupling in a direct-bonded interface for microelectronic devices | Oct 3, 2022 | Issued |