Search

Woo H. Choi

Supervisory Patent Examiner (ID: 7332, Phone: (571)272-4179 , Office: P/3992 )

Most Active Art Unit
3992
Art Unit(s)
2189, 2186, 3992
Total Applications
436
Issued Applications
307
Pending Applications
82
Abandoned Applications
52

Applications

Application numberTitle of the applicationFiling DateStatus
90/007780 METHOD AND APPARATUS FOR RECOGNIZING AND PERFORMING HANDWRITTEN CALCULATIONS Oct 23, 2005 Issued
Array ( [id] => 695245 [patent_doc_number] => 07076619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-11 [patent_title] => 'Storage system and method for reorganizing data to improve prefetch effectiveness and reduce seek distance' [patent_app_type] => utility [patent_app_number] => 11/237153 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/076/07076619.pdf [firstpage_image] =>[orig_patent_app_number] => 11237153 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/237153
Storage system and method for reorganizing data to improve prefetch effectiveness and reduce seek distance Sep 26, 2005 Issued
90/007611 CONTROLLER FOR A SYNCHRONOUS DRAM THAT MAXIMIZES THROUGHPUT BY ALLOWING MEMORY REQUESTS AND COMMANDS TO BE ISSUED OUT OF ORDER Jun 29, 2005 Issued
90/007532 MULTIPLIER ARRAY PROCESSING SYSTEM WITH ENHANCED UTILIZATION AT LOWER PRECISION May 3, 2005 Issued
Array ( [id] => 7232853 [patent_doc_number] => 20050262288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner' [patent_app_type] => utility [patent_app_number] => 11/121172 [patent_app_country] => US [patent_app_date] => 2005-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6366 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20050262288.pdf [firstpage_image] =>[orig_patent_app_number] => 11121172 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/121172
Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner May 3, 2005 Issued
Array ( [id] => 6976584 [patent_doc_number] => 20050286299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Flash memory and program verify method for flash memory' [patent_app_type] => utility [patent_app_number] => 11/116440 [patent_app_country] => US [patent_app_date] => 2005-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15822 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20050286299.pdf [firstpage_image] =>[orig_patent_app_number] => 11116440 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/116440
Flash memory and program verify method for flash memory Apr 27, 2005 Issued
Array ( [id] => 7188688 [patent_doc_number] => 20050162879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Automatic learning in a CAM' [patent_app_type] => utility [patent_app_number] => 11/085552 [patent_app_country] => US [patent_app_date] => 2005-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3897 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20050162879.pdf [firstpage_image] =>[orig_patent_app_number] => 11085552 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/085552
Automatic learning in a CAM Mar 21, 2005 Issued
Array ( [id] => 921908 [patent_doc_number] => 07325089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Controller for refreshing memories' [patent_app_type] => utility [patent_app_number] => 11/062768 [patent_app_country] => US [patent_app_date] => 2005-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2371 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/325/07325089.pdf [firstpage_image] =>[orig_patent_app_number] => 11062768 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/062768
Controller for refreshing memories Feb 21, 2005 Issued
Array ( [id] => 404156 [patent_doc_number] => 07293134 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-06 [patent_title] => 'System and method for an enhanced snapshot pointer' [patent_app_type] => utility [patent_app_number] => 11/026077 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6520 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/293/07293134.pdf [firstpage_image] =>[orig_patent_app_number] => 11026077 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/026077
System and method for an enhanced snapshot pointer Dec 29, 2004 Issued
Array ( [id] => 5809310 [patent_doc_number] => 20060095665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Real-time single hard disk data backup method' [patent_app_type] => utility [patent_app_number] => 10/980493 [patent_app_country] => US [patent_app_date] => 2004-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 744 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095665.pdf [firstpage_image] =>[orig_patent_app_number] => 10980493 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/980493
Real-time single hard disk data backup method Nov 1, 2004 Abandoned
Array ( [id] => 513029 [patent_doc_number] => 07206914 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-17 [patent_title] => 'Non-volatile memory system having a programmably selectable boot code section size' [patent_app_type] => utility [patent_app_number] => 10/968414 [patent_app_country] => US [patent_app_date] => 2004-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3481 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/206/07206914.pdf [firstpage_image] =>[orig_patent_app_number] => 10968414 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/968414
Non-volatile memory system having a programmably selectable boot code section size Oct 18, 2004 Issued
Array ( [id] => 7213996 [patent_doc_number] => 20050044307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Content addressable memory (CAM) device employing a recirculating shift register for data storage' [patent_app_type] => utility [patent_app_number] => 10/952728 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4017 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20050044307.pdf [firstpage_image] =>[orig_patent_app_number] => 10952728 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/952728
Content addressable memory (CAM) device employing a recirculating shift register for data storage Sep 29, 2004 Issued
Array ( [id] => 641089 [patent_doc_number] => 07127556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'Method and apparatus for initializing logical objects in a data storage system' [patent_app_type] => utility [patent_app_number] => 10/953936 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 19249 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/127/07127556.pdf [firstpage_image] =>[orig_patent_app_number] => 10953936 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/953936
Method and apparatus for initializing logical objects in a data storage system Sep 28, 2004 Issued
Array ( [id] => 7214215 [patent_doc_number] => 20050044337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Method and apparatus for address decoding of embedded DRAM devices' [patent_app_type] => utility [patent_app_number] => 10/952269 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2544 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20050044337.pdf [firstpage_image] =>[orig_patent_app_number] => 10952269 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/952269
Method and apparatus for address decoding of embedded DRAM devices Sep 27, 2004 Issued
Array ( [id] => 662912 [patent_doc_number] => 07107412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Distributed processor memory module and method' [patent_app_type] => utility [patent_app_number] => 10/928417 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2950 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/107/07107412.pdf [firstpage_image] =>[orig_patent_app_number] => 10928417 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/928417
Distributed processor memory module and method Aug 26, 2004 Issued
Array ( [id] => 7261893 [patent_doc_number] => 20040260875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Data storage system and method of hierarchical control thereof' [patent_app_type] => new [patent_app_number] => 10/898488 [patent_app_country] => US [patent_app_date] => 2004-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3599 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20040260875.pdf [firstpage_image] =>[orig_patent_app_number] => 10898488 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/898488
Data storage system and method of hierarchical control thereof Jul 22, 2004 Issued
Array ( [id] => 1024828 [patent_doc_number] => 06889292 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-03 [patent_title] => 'Methods and apparatus for accessing data using a cache' [patent_app_type] => utility [patent_app_number] => 10/875466 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 17756 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/889/06889292.pdf [firstpage_image] =>[orig_patent_app_number] => 10875466 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/875466
Methods and apparatus for accessing data using a cache Jun 23, 2004 Issued
Array ( [id] => 7449025 [patent_doc_number] => 20040268078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Detection of out of memory and graceful shutdown' [patent_app_type] => new [patent_app_number] => 10/874291 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4619 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20040268078.pdf [firstpage_image] =>[orig_patent_app_number] => 10874291 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/874291
Detection of out of memory and graceful shutdown Jun 23, 2004 Issued
Array ( [id] => 7091767 [patent_doc_number] => 20050010724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Method of controlling a cache memory, and corresponding cache memory device' [patent_app_type] => utility [patent_app_number] => 10/874804 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5889 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20050010724.pdf [firstpage_image] =>[orig_patent_app_number] => 10874804 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/874804
Method of controlling a cache memory, and corresponding cache memory device Jun 22, 2004 Abandoned
Array ( [id] => 457946 [patent_doc_number] => 07249230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Queue structure with validity vector and order array' [patent_app_type] => utility [patent_app_number] => 10/874998 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4119 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/249/07249230.pdf [firstpage_image] =>[orig_patent_app_number] => 10874998 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/874998
Queue structure with validity vector and order array Jun 22, 2004 Issued
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