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Wynn Wood Coggins

Examiner (ID: 16264)

Most Active Art Unit
3504
Art Unit(s)
2100, 2165, 3504, 3763, 3734, 3625, 3621, 2899
Total Applications
678
Issued Applications
614
Pending Applications
16
Abandoned Applications
48

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18897601 [patent_doc_number] => 20240013086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => SQUARE ARRAYS OF OCTAGONAL THREE-DIMENSIONAL MICROWAVE CAVITIES FOR QUANTUM COMPUTING [patent_app_type] => utility [patent_app_number] => 18/201476 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201476 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/201476
SQUARE ARRAYS OF OCTAGONAL THREE-DIMENSIONAL MICROWAVE CAVITIES FOR QUANTUM COMPUTING May 23, 2023 Pending
Array ( [id] => 19035963 [patent_doc_number] => 20240085778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => PHOTOMASK INCLUDING LINE PATTERN MONITORING MARK AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/318042 [patent_app_country] => US [patent_app_date] => 2023-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18318042 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/318042
PHOTOMASK INCLUDING LINE PATTERN MONITORING MARK AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE USING THE SAME May 15, 2023 Pending
Array ( [id] => 18599263 [patent_doc_number] => 20230274063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => METHOD OF MODELING A MASK BY TAKING INTO ACCOUNT OF MASK PATTERN EDGE INTERACTION [patent_app_type] => utility [patent_app_number] => 18/313705 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13093 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18313705 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/313705
METHOD OF MODELING A MASK BY TAKING INTO ACCOUNT OF MASK PATTERN EDGE INTERACTION May 7, 2023 Pending
Array ( [id] => 19115221 [patent_doc_number] => 20240126971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => LAYOUT DESIGN SYSTEM USING DEEP REINFORCEMENT LEARNING AND LEARNING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/124992 [patent_app_country] => US [patent_app_date] => 2023-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18124992 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/124992
LAYOUT DESIGN SYSTEM USING DEEP REINFORCEMENT LEARNING AND LEARNING METHOD THEREOF Mar 21, 2023 Pending
Array ( [id] => 18652323 [patent_doc_number] => 20230298159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => INTEGRATED CIRCUIT LAYOUT EXTRACTION USING PARALLELIZED TILE IMAGE PROCESSING [patent_app_type] => utility [patent_app_number] => 18/121069 [patent_app_country] => US [patent_app_date] => 2023-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18121069 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/121069
INTEGRATED CIRCUIT LAYOUT EXTRACTION USING PARALLELIZED TILE IMAGE PROCESSING Mar 13, 2023 Pending
Array ( [id] => 19383399 [patent_doc_number] => 20240273269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => METHODS AND APPARATUS TO IMPLEMENT LOCALIZED CONTEXT CONFIGURATION FOR ELECTRONIC DESIGN AUTOMATION [patent_app_type] => utility [patent_app_number] => 18/166974 [patent_app_country] => US [patent_app_date] => 2023-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166974 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/166974
METHODS AND APPARATUS TO IMPLEMENT LOCALIZED CONTEXT CONFIGURATION FOR ELECTRONIC DESIGN AUTOMATION Feb 8, 2023 Pending
Array ( [id] => 19334623 [patent_doc_number] => 20240249053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => TIMING ANALYSIS IN STACKED DIES [patent_app_type] => utility [patent_app_number] => 18/101098 [patent_app_country] => US [patent_app_date] => 2023-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18101098 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/101098
TIMING ANALYSIS IN STACKED DIES Jan 23, 2023 Pending
Array ( [id] => 18974182 [patent_doc_number] => 20240054274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => DUMMY METAL FILLING METHOD AND APPARATUS, DEVICE AND MEDIUM [patent_app_type] => utility [patent_app_number] => 18/155768 [patent_app_country] => US [patent_app_date] => 2023-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155768 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/155768
DUMMY METAL FILLING METHOD AND APPARATUS, DEVICE AND MEDIUM Jan 17, 2023 Pending
Array ( [id] => 19144946 [patent_doc_number] => 20240143882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => METHODS AND APPARATUS TO ELEVATE CIRCUIT NODES [patent_app_type] => utility [patent_app_number] => 17/977666 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17977666 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/977666
METHODS AND APPARATUS TO ELEVATE CIRCUIT NODES Oct 30, 2022 Pending
Array ( [id] => 18958921 [patent_doc_number] => 20240047248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => ADAPTIVE MODEL TRAINING FOR PROCESS CONTROL OF SEMICONDUCTOR MANUFACTURING EQUIPMENT [patent_app_type] => utility [patent_app_number] => 18/258497 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18258497 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/258497
ADAPTIVE MODEL TRAINING FOR PROCESS CONTROL OF SEMICONDUCTOR MANUFACTURING EQUIPMENT Dec 12, 2021 Pending
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