Search

Xiaochun L. Chen

Examiner (ID: 14210, Phone: (571)272-0941 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
782
Issued Applications
685
Pending Applications
74
Abandoned Applications
40

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20732963 [patent_doc_number] => 12640223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Reducing partial block programming using dynamic trim settings [patent_app_type] => utility [patent_app_number] => 18/676267 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1190 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676267 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/676267
Reducing partial block programming using dynamic trim settings May 27, 2024 Issued
Array ( [id] => 20189598 [patent_doc_number] => 12400721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Tracking RC time constant by wordline in memory devices [patent_app_type] => utility [patent_app_number] => 18/671835 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8355 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671835 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/671835
Tracking RC time constant by wordline in memory devices May 21, 2024 Issued
Array ( [id] => 19435762 [patent_doc_number] => 20240304260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND READ METHOD OF MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/666819 [patent_app_country] => US [patent_app_date] => 2024-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18666819 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/666819
Non-volatile memory device, memory system including the same and read method of memory system May 16, 2024 Issued
Array ( [id] => 20667370 [patent_doc_number] => 12609150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => Memory cell arrangements and method of operating a memory cell [patent_app_type] => utility [patent_app_number] => 18/662013 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 13249 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662013 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/662013
Memory cell arrangements and method of operating a memory cell May 12, 2024 Issued
Array ( [id] => 19406872 [patent_doc_number] => 20240290383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SYSTEM AND METHOD APPLIED WITH COMPUTING-IN-MEMORY [patent_app_type] => utility [patent_app_number] => 18/655591 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12204 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655591 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/655591
SYSTEM AND METHOD APPLIED WITH COMPUTING-IN-MEMORY May 5, 2024 Pending
Array ( [id] => 20389110 [patent_doc_number] => 12488843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Voltage generating circuit [patent_app_type] => utility [patent_app_number] => 18/639995 [patent_app_country] => US [patent_app_date] => 2024-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 947 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18639995 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/639995
Voltage generating circuit Apr 18, 2024 Issued
Array ( [id] => 20441333 [patent_doc_number] => 12512173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Memory circuit [patent_app_type] => utility [patent_app_number] => 18/640912 [patent_app_country] => US [patent_app_date] => 2024-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8333 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18640912 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/640912
Memory circuit Apr 18, 2024 Issued
Array ( [id] => 20611051 [patent_doc_number] => 12586656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Self-calibration in a memory device [patent_app_type] => utility [patent_app_number] => 18/638379 [patent_app_country] => US [patent_app_date] => 2024-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5917 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18638379 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/638379
Self-calibration in a memory device Apr 16, 2024 Issued
Array ( [id] => 19533912 [patent_doc_number] => 20240357814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => NOR Memory Array, NOR Memory and Electronic Device [patent_app_type] => utility [patent_app_number] => 18/633416 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11396 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633416 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/633416
NOR Memory Array, NOR Memory and Electronic Device Apr 10, 2024 Pending
Array ( [id] => 19850381 [patent_doc_number] => 20250095732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => MEMORY DEVICE AND INITIALIZING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/624884 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13565 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624884 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624884
MEMORY DEVICE AND INITIALIZING METHOD THEREOF Apr 1, 2024 Pending
Array ( [id] => 20538567 [patent_doc_number] => 12555646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Mode register update (MRUPD) mode [patent_app_type] => utility [patent_app_number] => 18/622900 [patent_app_country] => US [patent_app_date] => 2024-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 12022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622900 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/622900
Mode register update (MRUPD) mode Mar 29, 2024 Issued
Array ( [id] => 20746627 [patent_doc_number] => 12646546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-02 [patent_title] => Read for memory cell with threshold switching selector [patent_app_type] => utility [patent_app_number] => 18/620473 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 16267 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18620473 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/620473
Read for memory cell with threshold switching selector Mar 27, 2024 Issued
Array ( [id] => 19483742 [patent_doc_number] => 20240331784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => HALF GOOD BLOCK HANDLING WITH DEFECTIVE DECK PRE-PROGRAMING IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 18/619094 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18619094 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/619094
Half good block handling with defective deck pre-programing in a memory sub-system Mar 26, 2024 Issued
Array ( [id] => 19305212 [patent_doc_number] => 20240233792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => MEMORY DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/615866 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615866 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615866
MEMORY DEVICE AND METHOD Mar 24, 2024 Pending
Array ( [id] => 20375088 [patent_doc_number] => 12482530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Tracking and refreshing state metrics in memory sub-systems [patent_app_type] => utility [patent_app_number] => 18/605636 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18605636 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/605636
Tracking and refreshing state metrics in memory sub-systems Mar 13, 2024 Issued
Array ( [id] => 20718107 [patent_doc_number] => 12633363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Encoded read-only memory and decoder [patent_app_type] => utility [patent_app_number] => 18/605079 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18605079 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/605079
Encoded read-only memory and decoder Mar 13, 2024 Issued
Array ( [id] => 20820699 [patent_doc_number] => 12676172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-07 [patent_title] => Physically unclonable function cell and operation method of the same [patent_app_type] => utility [patent_app_number] => 18/600230 [patent_app_country] => US [patent_app_date] => 2024-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4503 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18600230 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/600230
Physically unclonable function cell and operation method of the same Mar 7, 2024 Issued
Array ( [id] => 20551939 [patent_doc_number] => 12562742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Method for processing input variables by means of a processing device having at least one transistor, device for executing the method, computing device and use [patent_app_type] => utility [patent_app_number] => 18/600281 [patent_app_country] => US [patent_app_date] => 2024-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 3059 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18600281 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/600281
Method for processing input variables by means of a processing device having at least one transistor, device for executing the method, computing device and use Mar 7, 2024 Issued
Array ( [id] => 19363927 [patent_doc_number] => 20240265961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => SIGNAL TIMING ALIGNMENT BASED ON A COMMON DATA STROBE IN MEMORY DEVICES CONFIGURED FOR STACKED ARRANGEMENTS [patent_app_type] => utility [patent_app_number] => 18/441517 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441517 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/441517
SIGNAL TIMING ALIGNMENT BASED ON A COMMON DATA STROBE IN MEMORY DEVICES CONFIGURED FOR STACKED ARRANGEMENTS Feb 13, 2024 Abandoned
Array ( [id] => 19926009 [patent_doc_number] => 12300301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Memory with partial array refresh [patent_app_type] => utility [patent_app_number] => 18/434404 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3670 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18434404 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/434404
Memory with partial array refresh Feb 5, 2024 Issued
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