Xiaoming Liu

Array ( [id] => 4279670 [patent_doc_number] => 06260046 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Product architecture retrieval information system' [patent_app_type] => 1 [patent_app_number] => 9/203878 [patent_app_country] => US [patent_app_date] => 1998-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2875 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260046.pdf [firstpage_image] =>[orig_patent_app_number] => 203878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7635031 [patent_doc_number] => 06381635 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Method for displaying multiple performance measurements of a web site using a platform independent program' [patent_app_type] => B1 [patent_app_number] => 09/195812 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9077 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381635.pdf [firstpage_image] =>[orig_patent_app_number] => 09195812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4209103 [patent_doc_number] => 06154829 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Cascaded arithmetic pipeline data processor' [patent_app_type] => 1 [patent_app_number] => 9/174562 [patent_app_country] => US [patent_app_date] => 1998-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9983 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154829.pdf [firstpage_image] =>[orig_patent_app_number] => 174562 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4422940 [patent_doc_number] => 06173408 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Processor' [patent_app_type] => 1 [patent_app_number] => 9/145646 [patent_app_country] => US [patent_app_date] => 1998-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 19 [patent_no_of_words] => 7574 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173408.pdf [firstpage_image] =>[orig_patent_app_number] => 145646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4310431 [patent_doc_number] => 06212623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Universal dependency vector/queue entry' [patent_app_type] => 1 [patent_app_number] => 9/139178 [patent_app_country] => US [patent_app_date] => 1998-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 15393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212623.pdf [firstpage_image] =>[orig_patent_app_number] => 139178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4147869 [patent_doc_number] => 06128727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Self modifying code to test all possible addressing modes' [patent_app_type] => 1 [patent_app_number] => 9/137610 [patent_app_country] => US [patent_app_date] => 1998-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4218 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128727.pdf [firstpage_image] =>[orig_patent_app_number] => 137610 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1414811 [patent_doc_number] => 06549933 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Managing, accessing, and retrieving networked information using physical objects associated with the networked information' [patent_app_type] => B1 [patent_app_number] => 09/128436 [patent_app_country] => US [patent_app_date] => 1998-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6925 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549933.pdf [firstpage_image] =>[orig_patent_app_number] => 09128436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4237476 [patent_doc_number] => 06112293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Processor configured to generate lookahead results from operand collapse unit and for inhibiting receipt/execution of the first instruction based on the lookahead result' [patent_app_type] => 1 [patent_app_number] => 9/115123 [patent_app_country] => US [patent_app_date] => 1998-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 17493 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112293.pdf [firstpage_image] =>[orig_patent_app_number] => 115123 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4203700 [patent_doc_number] => 06161171 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Apparatus for pipelining sequential instructions in synchronism with an operation clock' [patent_app_type] => 1 [patent_app_number] => 9/105212 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6660 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/161/06161171.pdf [firstpage_image] =>[orig_patent_app_number] => 105212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4310400 [patent_doc_number] => 06212621 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method and system using tagged instructions to allow out-of-program-order instruction decoding' [patent_app_type] => 1 [patent_app_number] => 9/104047 [patent_app_country] => US [patent_app_date] => 1998-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212621.pdf [firstpage_image] =>[orig_patent_app_number] => 104047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4324131 [patent_doc_number] => 06189092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Pipeline processor capable of reducing branch hazards with small-scale circuit' [patent_app_type] => 1 [patent_app_number] => 9/099299 [patent_app_country] => US [patent_app_date] => 1998-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7063 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/189/06189092.pdf [firstpage_image] =>[orig_patent_app_number] => 099299 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4160698 [patent_doc_number] => 06061778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Digital signal processor for detecting out-of-sync and jitter from two clock signals and controlling the interpolation based on deviation and jitter amount' [patent_app_type] => 1 [patent_app_number] => 9/088638 [patent_app_country] => US [patent_app_date] => 1998-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2253 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061778.pdf [firstpage_image] =>[orig_patent_app_number] => 088638 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4426937 [patent_doc_number] => 06195745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Pipeline throughput via parallel out-of-order execution of adds and moves in a supplemental integer execution unit' [patent_app_type] => 1 [patent_app_number] => 9/080492 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3990 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195745.pdf [firstpage_image] =>[orig_patent_app_number] => 080492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4256625 [patent_doc_number] => 06144995 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Data transfer method for logical computers' [patent_app_type] => 1 [patent_app_number] => 9/070841 [patent_app_country] => US [patent_app_date] => 1998-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2724 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144995.pdf [firstpage_image] =>[orig_patent_app_number] => 070841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4118444 [patent_doc_number] => 06098166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Speculative issue of instructions under a load miss shadow' [patent_app_type] => 1 [patent_app_number] => 9/058487 [patent_app_country] => US [patent_app_date] => 1998-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7986 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098166.pdf [firstpage_image] =>[orig_patent_app_number] => 058487 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4377862 [patent_doc_number] => 06192341 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Data processing system and method for customizing data processing system output for sense-impaired users' [patent_app_type] => 1 [patent_app_number] => 9/056116 [patent_app_country] => US [patent_app_date] => 1998-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4422 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192341.pdf [firstpage_image] =>[orig_patent_app_number] => 056116 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4179516 [patent_doc_number] => 06115812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method and apparatus for efficient vertical SIMD computations' [patent_app_type] => 1 [patent_app_number] => 9/053308 [patent_app_country] => US [patent_app_date] => 1998-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 10936 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115812.pdf [firstpage_image] =>[orig_patent_app_number] => 053308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4057866 [patent_doc_number] => 05996081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'System having series controllers for controlling suspending of power to associate core blocks based on suspending signal and signal indicators that the converted data is invalid' [patent_app_type] => 1 [patent_app_number] => 9/031680 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2488 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996081.pdf [firstpage_image] =>[orig_patent_app_number] => 031680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4379760 [patent_doc_number] => 06192461 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Method and apparatus for facilitating multiple storage instruction completions in a superscalar processor during a single clock cycle' [patent_app_type] => 1 [patent_app_number] => 9/016654 [patent_app_country] => US [patent_app_date] => 1998-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 11023 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192461.pdf [firstpage_image] =>[orig_patent_app_number] => 016654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4255295 [patent_doc_number] => 06119220 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method of and apparatus for supplying multiple instruction strings whose addresses are discontinued by branch instructions' [patent_app_type] => 1 [patent_app_number] => 9/015520 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 6671 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119220.pdf [firstpage_image] =>[orig_patent_app_number] => 015520 [rel_patent_id] =>[rel_patent_doc_number] =>)