Search

Xiaoming Liu

Examiner (ID: 12447, Phone: (571)270-0384 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
673
Issued Applications
518
Pending Applications
97
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18945644 [patent_doc_number] => 20240040783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => FLASH MEMORY WITH IREAD TUNING [patent_app_type] => utility [patent_app_number] => 17/877807 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10915 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877807 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/877807
FLASH MEMORY WITH IREAD TUNING Jul 28, 2022 Abandoned
Array ( [id] => 18024592 [patent_doc_number] => 20220376091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/875279 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17875279 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/875279
Method of manufacturing a semiconductor device and a semiconductor device Jul 26, 2022 Issued
Array ( [id] => 19277468 [patent_doc_number] => 12027601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Method for forming semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/815253 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 7098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815253 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815253
Method for forming semiconductor structure Jul 26, 2022 Issued
Array ( [id] => 17993661 [patent_doc_number] => 20220359698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SEMICONDUCTOR DEVICE WITH MULTI-THRESHOLD GATE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/870554 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870554 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/870554
Semiconductor device with multi-threshold gate structure Jul 20, 2022 Issued
Array ( [id] => 17993723 [patent_doc_number] => 20220359760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => FLASH MEMORY DEVICE WITH THREE-DIMENSIONAL HALF FLASH STRUCTURE AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/868192 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868192 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/868192
Flash memory device with three-dimensional half flash structure and methods for forming the same Jul 18, 2022 Issued
Array ( [id] => 18920381 [patent_doc_number] => 11882691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Methods of fabricating semiconductor device [patent_app_type] => utility [patent_app_number] => 17/858361 [patent_app_country] => US [patent_app_date] => 2022-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 61 [patent_no_of_words] => 9187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17858361 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/858361
Methods of fabricating semiconductor device Jul 5, 2022 Issued
Array ( [id] => 17949615 [patent_doc_number] => 20220336634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => SOURCE ELECTRODE AND DRAIN ELECTRODE PROTECTION FOR NANOWIRE TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/853320 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853320 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/853320
Source electrode and drain electrode protection for nanowire transistors Jun 28, 2022 Issued
Array ( [id] => 18307954 [patent_doc_number] => 20230111854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/851245 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851245 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/851245
Semiconductor package Jun 27, 2022 Issued
Array ( [id] => 18983549 [patent_doc_number] => 11908737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Method of manufacturing semiconductor device, substrate processing apparatus and recording medium [patent_app_type] => utility [patent_app_number] => 17/842409 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 11227 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842409 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842409
Method of manufacturing semiconductor device, substrate processing apparatus and recording medium Jun 15, 2022 Issued
Array ( [id] => 20148478 [patent_doc_number] => 12382840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Damascene MRAM device [patent_app_type] => utility [patent_app_number] => 17/806511 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 1119 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806511 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/806511
Damascene MRAM device Jun 12, 2022 Issued
Array ( [id] => 18833990 [patent_doc_number] => 20230402517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/835965 [patent_app_country] => US [patent_app_date] => 2022-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17835965 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/835965
Semiconductor memory device and fabrication method thereof Jun 8, 2022 Issued
Array ( [id] => 19124821 [patent_doc_number] => 11968829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Method of forming memory cells, high voltage devices and logic devices on a semiconductor substrate [patent_app_type] => utility [patent_app_number] => 17/834746 [patent_app_country] => US [patent_app_date] => 2022-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 46 [patent_no_of_words] => 5504 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 624 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834746 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/834746
Method of forming memory cells, high voltage devices and logic devices on a semiconductor substrate Jun 6, 2022 Issued
Array ( [id] => 17886793 [patent_doc_number] => 20220302271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => HIGH POWER TRANSISTOR WITH INTERIOR-FED FINGERS [patent_app_type] => utility [patent_app_number] => 17/834421 [patent_app_country] => US [patent_app_date] => 2022-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834421 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/834421
High power transistor with interior-fed fingers Jun 6, 2022 Issued
Array ( [id] => 19094057 [patent_doc_number] => 11955524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Semi-floating gate device [patent_app_type] => utility [patent_app_number] => 17/828299 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6592 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 442 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828299 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/828299
Semi-floating gate device May 30, 2022 Issued
Array ( [id] => 19524169 [patent_doc_number] => 12125910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Transistor structure with increased gate dielectric thickness between gate-to-drain overlap region [patent_app_type] => utility [patent_app_number] => 17/828304 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 41 [patent_no_of_words] => 9471 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828304 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/828304
Transistor structure with increased gate dielectric thickness between gate-to-drain overlap region May 30, 2022 Issued
Array ( [id] => 17855479 [patent_doc_number] => 20220285522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => METHOD FOR FORMING A HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/824917 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824917 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824917
Method for forming a high-voltage metal-oxide-semiconductor transistor device May 25, 2022 Issued
Array ( [id] => 18848947 [patent_doc_number] => 20230411351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => Circuits and Methods for I/O Circuitry TSV Coupling [patent_app_type] => utility [patent_app_number] => 17/752560 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9565 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752560 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/752560
Circuits and Methods for I/O Circuitry TSV Coupling May 23, 2022 Pending
Array ( [id] => 18679907 [patent_doc_number] => 20230317565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/750711 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750711 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750711
ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF May 22, 2022 Pending
Array ( [id] => 17810805 [patent_doc_number] => 20220262640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => METHOD FOR PREVENTING LINE BENDING DURING METAL FILL PROCESS [patent_app_type] => utility [patent_app_number] => 17/662220 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19543 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17662220 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/662220
Method for preventing line bending during metal fill process May 4, 2022 Issued
Array ( [id] => 19349474 [patent_doc_number] => 20240258438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SEMICONDUCTOR DIODE [patent_app_type] => utility [patent_app_number] => 18/566079 [patent_app_country] => US [patent_app_date] => 2022-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7341 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18566079 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/566079
SEMICONDUCTOR DIODE Apr 21, 2022 Pending
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