Search

Xiuqin Sun

Examiner (ID: 6335, Phone: (571)272-2280 , Office: P/2863 )

Most Active Art Unit
2863
Art Unit(s)
2862, 2863, 2857
Total Applications
1009
Issued Applications
722
Pending Applications
79
Abandoned Applications
220

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4204578 [patent_doc_number] => 06077733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Method of manufacturing self-aligned T-shaped gate through dual damascene' [patent_app_type] => 1 [patent_app_number] => 9/389885 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3649 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/077/06077733.pdf [firstpage_image] =>[orig_patent_app_number] => 389885 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389885
Method of manufacturing self-aligned T-shaped gate through dual damascene Sep 2, 1999 Issued
Array ( [id] => 4113841 [patent_doc_number] => 06046081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Method for forming dielectric layer of capacitor' [patent_app_type] => 1 [patent_app_number] => 9/330246 [patent_app_country] => US [patent_app_date] => 1999-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1707 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046081.pdf [firstpage_image] =>[orig_patent_app_number] => 330246 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/330246
Method for forming dielectric layer of capacitor Jun 9, 1999 Issued
Array ( [id] => 4214886 [patent_doc_number] => 06087196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Fabrication of organic semiconductor devices using ink jet printing' [patent_app_type] => 1 [patent_app_number] => 9/238708 [patent_app_country] => US [patent_app_date] => 1999-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 34 [patent_no_of_words] => 3657 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087196.pdf [firstpage_image] =>[orig_patent_app_number] => 238708 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238708
Fabrication of organic semiconductor devices using ink jet printing Jan 27, 1999 Issued
Array ( [id] => 4218744 [patent_doc_number] => 06040207 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Oxide formation technique using thin film silicon deposition' [patent_app_type] => 1 [patent_app_number] => 9/189278 [patent_app_country] => US [patent_app_date] => 1998-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 4246 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040207.pdf [firstpage_image] =>[orig_patent_app_number] => 189278 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/189278
Oxide formation technique using thin film silicon deposition Nov 9, 1998 Issued
Array ( [id] => 4219022 [patent_doc_number] => 06040227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'IPO deposited with low pressure O.sub.3 -TEOS for planarization in multi-poly memory technology' [patent_app_type] => 1 [patent_app_number] => 9/086826 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3543 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040227.pdf [firstpage_image] =>[orig_patent_app_number] => 086826 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086826
IPO deposited with low pressure O.sub.3 -TEOS for planarization in multi-poly memory technology May 28, 1998 Issued
Array ( [id] => 3944614 [patent_doc_number] => 05998293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect' [patent_app_type] => 1 [patent_app_number] => 9/067425 [patent_app_country] => US [patent_app_date] => 1998-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3410 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998293.pdf [firstpage_image] =>[orig_patent_app_number] => 067425 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/067425
Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect Apr 27, 1998 Issued
Array ( [id] => 4152297 [patent_doc_number] => 06124186 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Deposition of device quality, low hydrogen content, hydrogenated amorphous silicon at high deposition rates with increased stability using the hot wire filament technique' [patent_app_type] => 1 [patent_app_number] => 9/066276 [patent_app_country] => US [patent_app_date] => 1998-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10108 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124186.pdf [firstpage_image] =>[orig_patent_app_number] => 066276 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/066276
Deposition of device quality, low hydrogen content, hydrogenated amorphous silicon at high deposition rates with increased stability using the hot wire filament technique Apr 23, 1998 Issued
Array ( [id] => 4215053 [patent_doc_number] => 06087208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method for increasing gate capacitance by using both high and low dielectric gate material' [patent_app_type] => 1 [patent_app_number] => 9/052386 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 5271 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087208.pdf [firstpage_image] =>[orig_patent_app_number] => 052386 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052386
Method for increasing gate capacitance by using both high and low dielectric gate material Mar 30, 1998 Issued
Array ( [id] => 4009479 [patent_doc_number] => 05920792 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'High density plasma enhanced chemical vapor deposition process in combination with chemical mechanical polishing process for preparation and planarization of intemetal dielectric layers' [patent_app_type] => 1 [patent_app_number] => 9/045101 [patent_app_country] => US [patent_app_date] => 1998-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4047 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920792.pdf [firstpage_image] =>[orig_patent_app_number] => 045101 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/045101
High density plasma enhanced chemical vapor deposition process in combination with chemical mechanical polishing process for preparation and planarization of intemetal dielectric layers Mar 18, 1998 Issued
Array ( [id] => 3942477 [patent_doc_number] => 05946592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Combined in-situ high density plasma enhanced chemical vapor deposition (HDPCVD) and chemical mechanical polishing (CMP) process to form an intermetal dielectric layer with a stopper layer embedded therein' [patent_app_type] => 1 [patent_app_number] => 9/044970 [patent_app_country] => US [patent_app_date] => 1998-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4146 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946592.pdf [firstpage_image] =>[orig_patent_app_number] => 044970 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/044970
Combined in-situ high density plasma enhanced chemical vapor deposition (HDPCVD) and chemical mechanical polishing (CMP) process to form an intermetal dielectric layer with a stopper layer embedded therein Mar 18, 1998 Issued
Array ( [id] => 4204876 [patent_doc_number] => 06077754 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Methods of forming a silicon nitride film, a capacitor dielectric layer and a capacitor' [patent_app_type] => 1 [patent_app_number] => 9/018925 [patent_app_country] => US [patent_app_date] => 1998-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2380 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/077/06077754.pdf [firstpage_image] =>[orig_patent_app_number] => 018925 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/018925
Methods of forming a silicon nitride film, a capacitor dielectric layer and a capacitor Feb 4, 1998 Issued
Array ( [id] => 4094516 [patent_doc_number] => 06096597 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method for fabricating an integrated circuit structure' [patent_app_type] => 1 [patent_app_number] => 9/014204 [patent_app_country] => US [patent_app_date] => 1998-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 5634 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096597.pdf [firstpage_image] =>[orig_patent_app_number] => 014204 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/014204
Method for fabricating an integrated circuit structure Jan 27, 1998 Issued
Array ( [id] => 4153440 [patent_doc_number] => 06107168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Process for passivating a silicon carbide surface against oxygen' [patent_app_type] => 1 [patent_app_number] => 8/945155 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1966 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107168.pdf [firstpage_image] =>[orig_patent_app_number] => 945155 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/945155
Process for passivating a silicon carbide surface against oxygen Dec 17, 1997 Issued
Array ( [id] => 4106905 [patent_doc_number] => 06022799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Methods for making a semiconductor device with improved hot carrier lifetime' [patent_app_type] => 1 [patent_app_number] => 8/993828 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3231 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/022/06022799.pdf [firstpage_image] =>[orig_patent_app_number] => 993828 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993828
Methods for making a semiconductor device with improved hot carrier lifetime Dec 17, 1997 Issued
Array ( [id] => 4085426 [patent_doc_number] => 06017786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Method for forming a low barrier height oxide layer on a silicon substrate' [patent_app_type] => 1 [patent_app_number] => 8/982186 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 2257 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/017/06017786.pdf [firstpage_image] =>[orig_patent_app_number] => 982186 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982186
Method for forming a low barrier height oxide layer on a silicon substrate Dec 16, 1997 Issued
Array ( [id] => 4233362 [patent_doc_number] => 06074885 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Lead titanate isolation layers for use in fabricating PZT-based capacitors and similar structures' [patent_app_type] => 1 [patent_app_number] => 8/978308 [patent_app_country] => US [patent_app_date] => 1997-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1876 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074885.pdf [firstpage_image] =>[orig_patent_app_number] => 978308 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/978308
Lead titanate isolation layers for use in fabricating PZT-based capacitors and similar structures Nov 24, 1997 Issued
Array ( [id] => 4084554 [patent_doc_number] => 06025228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Method of fabricating an oxynitride-capped high dielectric constant interpolysilicon dielectric structure for a low voltage non-volatile memory' [patent_app_type] => 1 [patent_app_number] => 8/978398 [patent_app_country] => US [patent_app_date] => 1997-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2953 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025228.pdf [firstpage_image] =>[orig_patent_app_number] => 978398 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/978398
Method of fabricating an oxynitride-capped high dielectric constant interpolysilicon dielectric structure for a low voltage non-volatile memory Nov 24, 1997 Issued
Array ( [id] => 3937251 [patent_doc_number] => 05915201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Trench surrounded metal pattern' [patent_app_type] => 1 [patent_app_number] => 8/960771 [patent_app_country] => US [patent_app_date] => 1997-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2525 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915201.pdf [firstpage_image] =>[orig_patent_app_number] => 960771 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/960771
Trench surrounded metal pattern Oct 29, 1997 Issued
Array ( [id] => 4042739 [patent_doc_number] => 05874368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Silicon nitride from bis(tertiarybutylamino)silane' [patent_app_type] => 1 [patent_app_number] => 8/942996 [patent_app_country] => US [patent_app_date] => 1997-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4588 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/874/05874368.pdf [firstpage_image] =>[orig_patent_app_number] => 942996 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/942996
Silicon nitride from bis(tertiarybutylamino)silane Oct 1, 1997 Issued
Array ( [id] => 3825754 [patent_doc_number] => 05783482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Method to prevent oxide peeling induced by sog etchback on the wafer edge' [patent_app_type] => 1 [patent_app_number] => 8/928228 [patent_app_country] => US [patent_app_date] => 1997-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1734 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/783/05783482.pdf [firstpage_image] =>[orig_patent_app_number] => 928228 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/928228
Method to prevent oxide peeling induced by sog etchback on the wafer edge Sep 11, 1997 Issued
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