Search

Xuan Marian Thai

Examiner (ID: 451)

Most Active Art Unit
3715
Art Unit(s)
2781, 3714, 3713, 3403, 3715, 2181, 2111, 2782
Total Applications
775
Issued Applications
391
Pending Applications
172
Abandoned Applications
214

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7630022 [patent_doc_number] => 06636917 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Card design having tape and disk drives' [patent_app_type] => B1 [patent_app_number] => 09/539759 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5438 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636917.pdf [firstpage_image] =>[orig_patent_app_number] => 09539759 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/539759
Card design having tape and disk drives Mar 30, 2000 Issued
Array ( [id] => 1431357 [patent_doc_number] => 06519664 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Parallel terminated bus system' [patent_app_type] => B1 [patent_app_number] => 09/539640 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 5070 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519664.pdf [firstpage_image] =>[orig_patent_app_number] => 09539640 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/539640
Parallel terminated bus system Mar 29, 2000 Issued
Array ( [id] => 1521679 [patent_doc_number] => 06502158 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Method and system for address spaces' [patent_app_type] => B1 [patent_app_number] => 09/531084 [patent_app_country] => US [patent_app_date] => 2000-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5248 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502158.pdf [firstpage_image] =>[orig_patent_app_number] => 09531084 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531084
Method and system for address spaces Mar 17, 2000 Issued
Array ( [id] => 7645914 [patent_doc_number] => 06477609 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Bridge state-machine progression for data transfers requested by a host bus and responded to by an external bus' [patent_app_type] => B1 [patent_app_number] => 09/495043 [patent_app_country] => US [patent_app_date] => 2000-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9462 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477609.pdf [firstpage_image] =>[orig_patent_app_number] => 09495043 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/495043
Bridge state-machine progression for data transfers requested by a host bus and responded to by an external bus Jan 30, 2000 Issued
Array ( [id] => 1505940 [patent_doc_number] => 06487625 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Circuit and method for achieving hold time compatability between data-source devices coupled to a data-requesting device through a data bus' [patent_app_type] => B1 [patent_app_number] => 09/478133 [patent_app_country] => US [patent_app_date] => 2000-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1795 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487625.pdf [firstpage_image] =>[orig_patent_app_number] => 09478133 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/478133
Circuit and method for achieving hold time compatability between data-source devices coupled to a data-requesting device through a data bus Jan 4, 2000 Issued
Array ( [id] => 1425110 [patent_doc_number] => 06535946 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Low-latency circuit for synchronizing data transfers between clock domains derived from a common clock' [patent_app_type] => B1 [patent_app_number] => 09/477321 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535946.pdf [firstpage_image] =>[orig_patent_app_number] => 09477321 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477321
Low-latency circuit for synchronizing data transfers between clock domains derived from a common clock Jan 3, 2000 Issued
Array ( [id] => 1234198 [patent_doc_number] => 06697896 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Method and apparatus for implementing high speed signals using differential reference signals' [patent_app_type] => B1 [patent_app_number] => 09/476614 [patent_app_country] => US [patent_app_date] => 1999-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3865 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697896.pdf [firstpage_image] =>[orig_patent_app_number] => 09476614 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476614
Method and apparatus for implementing high speed signals using differential reference signals Dec 30, 1999 Issued
Array ( [id] => 1366164 [patent_doc_number] => 06584522 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => 'Communication between processors' [patent_app_type] => B1 [patent_app_number] => 09/475609 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 2504 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/584/06584522.pdf [firstpage_image] =>[orig_patent_app_number] => 09475609 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475609
Communication between processors Dec 29, 1999 Issued
Array ( [id] => 1165491 [patent_doc_number] => 06772257 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Method and apparatus for processing interrupts' [patent_app_type] => B1 [patent_app_number] => 09/471941 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2440 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772257.pdf [firstpage_image] =>[orig_patent_app_number] => 09471941 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471941
Method and apparatus for processing interrupts Dec 22, 1999 Issued
Array ( [id] => 1236207 [patent_doc_number] => 06694394 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'Physical layer and data link interface with PHY detection' [patent_app_type] => B1 [patent_app_number] => 09/470680 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4880 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/694/06694394.pdf [firstpage_image] =>[orig_patent_app_number] => 09470680 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470680
Physical layer and data link interface with PHY detection Dec 22, 1999 Issued
Array ( [id] => 1210315 [patent_doc_number] => 06718417 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Physical layer and data link interface with flexible bus width' [patent_app_type] => B1 [patent_app_number] => 09/471791 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4880 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/718/06718417.pdf [firstpage_image] =>[orig_patent_app_number] => 09471791 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471791
Physical layer and data link interface with flexible bus width Dec 22, 1999 Issued
Array ( [id] => 1505945 [patent_doc_number] => 06487627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Method and apparatus to manage digital bus traffic' [patent_app_type] => B1 [patent_app_number] => 09/470539 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4391 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487627.pdf [firstpage_image] =>[orig_patent_app_number] => 09470539 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470539
Method and apparatus to manage digital bus traffic Dec 21, 1999 Issued
Array ( [id] => 1418586 [patent_doc_number] => 06546450 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Method and apparatus for sharing a universal serial bus device among multiple computers by switching' [patent_app_type] => B1 [patent_app_number] => 09/469659 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2953 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546450.pdf [firstpage_image] =>[orig_patent_app_number] => 09469659 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/469659
Method and apparatus for sharing a universal serial bus device among multiple computers by switching Dec 21, 1999 Issued
Array ( [id] => 771259 [patent_doc_number] => 07010629 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-07 [patent_title] => 'Apparatus and method for coupling to a memory module' [patent_app_type] => utility [patent_app_number] => 09/470542 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2405 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/010/07010629.pdf [firstpage_image] =>[orig_patent_app_number] => 09470542 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470542
Apparatus and method for coupling to a memory module Dec 21, 1999 Issued
Array ( [id] => 7644153 [patent_doc_number] => 06473821 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Multiple processor interface, synchronization, and arbitration scheme using time multiplexed shared memory for real time systems' [patent_app_type] => B1 [patent_app_number] => 09/468144 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2924 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473821.pdf [firstpage_image] =>[orig_patent_app_number] => 09468144 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/468144
Multiple processor interface, synchronization, and arbitration scheme using time multiplexed shared memory for real time systems Dec 20, 1999 Issued
Array ( [id] => 1409139 [patent_doc_number] => 06557065 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'CPU expandability bus' [patent_app_type] => B1 [patent_app_number] => 09/466890 [patent_app_country] => US [patent_app_date] => 1999-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3041 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557065.pdf [firstpage_image] =>[orig_patent_app_number] => 09466890 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/466890
CPU expandability bus Dec 19, 1999 Issued
Array ( [id] => 7644155 [patent_doc_number] => 06473819 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Scalable interruptible queue locks for shared-memory multiprocessor' [patent_app_type] => B1 [patent_app_number] => 09/465297 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4660 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473819.pdf [firstpage_image] =>[orig_patent_app_number] => 09465297 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/465297
Scalable interruptible queue locks for shared-memory multiprocessor Dec 16, 1999 Issued
Array ( [id] => 1471900 [patent_doc_number] => 06460109 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Integral portable computer input and output switching' [patent_app_type] => B1 [patent_app_number] => 09/464844 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6817 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460109.pdf [firstpage_image] =>[orig_patent_app_number] => 09464844 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/464844
Integral portable computer input and output switching Dec 15, 1999 Issued
Array ( [id] => 1430285 [patent_doc_number] => 06526468 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Peripheral bus extender' [patent_app_type] => B1 [patent_app_number] => 09/461045 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2802 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526468.pdf [firstpage_image] =>[orig_patent_app_number] => 09461045 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/461045
Peripheral bus extender Dec 14, 1999 Issued
Array ( [id] => 1260406 [patent_doc_number] => 06668297 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-23 [patent_title] => 'POS-PHY interface for interconnection of physical layer devices and link layer devices' [patent_app_type] => B1 [patent_app_number] => 09/459972 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7285 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/668/06668297.pdf [firstpage_image] =>[orig_patent_app_number] => 09459972 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/459972
POS-PHY interface for interconnection of physical layer devices and link layer devices Dec 13, 1999 Issued
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