Search

Xuan Marian Thai

Examiner (ID: 451)

Most Active Art Unit
3715
Art Unit(s)
2781, 3714, 3713, 3403, 3715, 2181, 2111, 2782
Total Applications
775
Issued Applications
391
Pending Applications
172
Abandoned Applications
214

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1501479 [patent_doc_number] => 06405270 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method and apparatus for increasing data rates between nodes of a serial bus' [patent_app_type] => B1 [patent_app_number] => 09/392039 [patent_app_country] => US [patent_app_date] => 1999-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4361 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405270.pdf [firstpage_image] =>[orig_patent_app_number] => 09392039 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/392039
Method and apparatus for increasing data rates between nodes of a serial bus Sep 7, 1999 Issued
Array ( [id] => 7638643 [patent_doc_number] => 06397278 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Bus construction' [patent_app_type] => B1 [patent_app_number] => 09/390589 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1694 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397278.pdf [firstpage_image] =>[orig_patent_app_number] => 09390589 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/390589
Bus construction Sep 2, 1999 Issued
Array ( [id] => 7638633 [patent_doc_number] => 06397288 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Rf PC interface' [patent_app_type] => B1 [patent_app_number] => 09/390540 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2759 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397288.pdf [firstpage_image] =>[orig_patent_app_number] => 09390540 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/390540
Rf PC interface Sep 2, 1999 Issued
Array ( [id] => 1423344 [patent_doc_number] => 06539444 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Information processing apparatus having a bus using the protocol of the acknowledge type in the source clock synchronous system' [patent_app_type] => B1 [patent_app_number] => 09/389227 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 3741 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539444.pdf [firstpage_image] =>[orig_patent_app_number] => 09389227 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389227
Information processing apparatus having a bus using the protocol of the acknowledge type in the source clock synchronous system Sep 2, 1999 Issued
Array ( [id] => 1573702 [patent_doc_number] => 06499072 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Data bus bandwidth allocation apparatus and method' [patent_app_type] => B1 [patent_app_number] => 09/388975 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2933 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499072.pdf [firstpage_image] =>[orig_patent_app_number] => 09388975 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/388975
Data bus bandwidth allocation apparatus and method Sep 1, 1999 Issued
Array ( [id] => 7642403 [patent_doc_number] => 06430643 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method and system for assigning interrupts among multiple interrupt presentation controllers' [patent_app_type] => B1 [patent_app_number] => 09/389438 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5126 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430643.pdf [firstpage_image] =>[orig_patent_app_number] => 09389438 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389438
Method and system for assigning interrupts among multiple interrupt presentation controllers Sep 1, 1999 Issued
Array ( [id] => 7638641 [patent_doc_number] => 06397280 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Slave station, master station, bus system and method for operating a bus' [patent_app_type] => B1 [patent_app_number] => 09/308486 [patent_app_country] => US [patent_app_date] => 1999-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6299 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397280.pdf [firstpage_image] =>[orig_patent_app_number] => 09308486 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/308486
Slave station, master station, bus system and method for operating a bus Jul 22, 1999 Issued
Array ( [id] => 1097272 [patent_doc_number] => 06826638 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Modular bay enclosure removable card method and system' [patent_app_type] => B1 [patent_app_number] => 09/353938 [patent_app_country] => US [patent_app_date] => 1999-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3474 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826638.pdf [firstpage_image] =>[orig_patent_app_number] => 09353938 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/353938
Modular bay enclosure removable card method and system Jul 14, 1999 Issued
Array ( [id] => 1466398 [patent_doc_number] => 06393570 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Low-power apparatus for power management enabling' [patent_app_type] => B1 [patent_app_number] => 09/322378 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4745 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393570.pdf [firstpage_image] =>[orig_patent_app_number] => 09322378 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322378
Low-power apparatus for power management enabling May 27, 1999 Issued
Array ( [id] => 1481232 [patent_doc_number] => 06389544 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Power monitoring method for a printer or other peripheral device, power monitoring apparatus, software program and information recording medium' [patent_app_type] => B1 [patent_app_number] => 09/322263 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5830 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389544.pdf [firstpage_image] =>[orig_patent_app_number] => 09322263 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322263
Power monitoring method for a printer or other peripheral device, power monitoring apparatus, software program and information recording medium May 27, 1999 Issued
Array ( [id] => 1409152 [patent_doc_number] => 06557066 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Method and apparatus for data dependent, dual level output driver' [patent_app_type] => B1 [patent_app_number] => 09/322328 [patent_app_country] => US [patent_app_date] => 1999-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 12346 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557066.pdf [firstpage_image] =>[orig_patent_app_number] => 09322328 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322328
Method and apparatus for data dependent, dual level output driver May 24, 1999 Issued
Array ( [id] => 1508967 [patent_doc_number] => 06467007 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Processor reset generated via memory access interrupt' [patent_app_type] => B1 [patent_app_number] => 09/314769 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5442 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467007.pdf [firstpage_image] =>[orig_patent_app_number] => 09314769 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314769
Processor reset generated via memory access interrupt May 18, 1999 Issued
Array ( [id] => 1432373 [patent_doc_number] => 06505265 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Bus arbitration system with changing arbitration rules' [patent_app_type] => B1 [patent_app_number] => 09/313279 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 44 [patent_no_of_words] => 15883 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505265.pdf [firstpage_image] =>[orig_patent_app_number] => 09313279 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/313279
Bus arbitration system with changing arbitration rules May 17, 1999 Issued
Array ( [id] => 1526444 [patent_doc_number] => 06353869 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Adaptive delay of polling frequencies in a distributed system with a queued lock' [patent_app_type] => B1 [patent_app_number] => 09/312146 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8021 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353869.pdf [firstpage_image] =>[orig_patent_app_number] => 09312146 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/312146
Adaptive delay of polling frequencies in a distributed system with a queued lock May 13, 1999 Issued
Array ( [id] => 1480976 [patent_doc_number] => 06389501 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'I/O peripheral device for use in a store-and-forward segment of a peripheral bus' [patent_app_type] => B1 [patent_app_number] => 09/309087 [patent_app_country] => US [patent_app_date] => 1999-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6188 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389501.pdf [firstpage_image] =>[orig_patent_app_number] => 09309087 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/309087
I/O peripheral device for use in a store-and-forward segment of a peripheral bus May 9, 1999 Issued
Array ( [id] => 1604470 [patent_doc_number] => 06434656 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method for routing I/O data in a multiprocessor system having a non-uniform memory access architecture' [patent_app_type] => B1 [patent_app_number] => 09/307132 [patent_app_country] => US [patent_app_date] => 1999-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434656.pdf [firstpage_image] =>[orig_patent_app_number] => 09307132 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/307132
Method for routing I/O data in a multiprocessor system having a non-uniform memory access architecture May 6, 1999 Issued
Array ( [id] => 1513186 [patent_doc_number] => 06442631 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Allocating system resources based upon priority' [patent_app_type] => B1 [patent_app_number] => 09/306878 [patent_app_country] => US [patent_app_date] => 1999-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4048 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442631.pdf [firstpage_image] =>[orig_patent_app_number] => 09306878 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/306878
Allocating system resources based upon priority May 6, 1999 Issued
Array ( [id] => 1423368 [patent_doc_number] => 06539446 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Resource locking approach' [patent_app_type] => B1 [patent_app_number] => 09/307043 [patent_app_country] => US [patent_app_date] => 1999-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7097 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539446.pdf [firstpage_image] =>[orig_patent_app_number] => 09307043 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/307043
Resource locking approach May 6, 1999 Issued
Array ( [id] => 4324866 [patent_doc_number] => 06327664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Power management on a memory card having a signal processing element' [patent_app_type] => 1 [patent_app_number] => 9/302916 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3842 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327664.pdf [firstpage_image] =>[orig_patent_app_number] => 302916 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302916
Power management on a memory card having a signal processing element Apr 29, 1999 Issued
Array ( [id] => 1495436 [patent_doc_number] => 06418535 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Bi-level power saver method for portable or laptop computer' [patent_app_type] => B1 [patent_app_number] => 09/301290 [patent_app_country] => US [patent_app_date] => 1999-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3199 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418535.pdf [firstpage_image] =>[orig_patent_app_number] => 09301290 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/301290
Bi-level power saver method for portable or laptop computer Apr 27, 1999 Issued
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