Search

Xuan Marian Thai

Examiner (ID: 451)

Most Active Art Unit
3715
Art Unit(s)
2781, 3714, 3713, 3403, 3715, 2181, 2111, 2782
Total Applications
775
Issued Applications
391
Pending Applications
172
Abandoned Applications
214

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1430026 [patent_doc_number] => 06510525 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Method and apparatus to power up an integrated device from a low power state' [patent_app_type] => B1 [patent_app_number] => 09/300075 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8072 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510525.pdf [firstpage_image] =>[orig_patent_app_number] => 09300075 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/300075
Method and apparatus to power up an integrated device from a low power state Apr 25, 1999 Issued
Array ( [id] => 1431371 [patent_doc_number] => 06523124 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'System and method for detection of an accessory device connection status' [patent_app_type] => B1 [patent_app_number] => 09/298113 [patent_app_country] => US [patent_app_date] => 1999-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6253 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523124.pdf [firstpage_image] =>[orig_patent_app_number] => 09298113 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/298113
System and method for detection of an accessory device connection status Apr 22, 1999 Issued
Array ( [id] => 1552730 [patent_doc_number] => 06446146 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Line terminating device' [patent_app_type] => B1 [patent_app_number] => 09/296841 [patent_app_country] => US [patent_app_date] => 1999-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 3617 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446146.pdf [firstpage_image] =>[orig_patent_app_number] => 09296841 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/296841
Line terminating device Apr 21, 1999 Issued
Array ( [id] => 1567523 [patent_doc_number] => 06438686 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method and apparatus for eliminating contention with dual bus masters' [patent_app_type] => B1 [patent_app_number] => 09/296195 [patent_app_country] => US [patent_app_date] => 1999-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3300 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438686.pdf [firstpage_image] =>[orig_patent_app_number] => 09296195 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/296195
Method and apparatus for eliminating contention with dual bus masters Apr 19, 1999 Issued
Array ( [id] => 1481807 [patent_doc_number] => 06345362 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Managing Vt for reduced power using a status table' [patent_app_type] => B1 [patent_app_number] => 09/287173 [patent_app_country] => US [patent_app_date] => 1999-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5590 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/345/06345362.pdf [firstpage_image] =>[orig_patent_app_number] => 09287173 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/287173
Managing Vt for reduced power using a status table Apr 5, 1999 Issued
Array ( [id] => 7645869 [patent_doc_number] => 06477654 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Managing VT for reduced power using power setting commands in the instruction stream' [patent_app_type] => B1 [patent_app_number] => 09/287159 [patent_app_country] => US [patent_app_date] => 1999-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4052 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477654.pdf [firstpage_image] =>[orig_patent_app_number] => 09287159 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/287159
Managing VT for reduced power using power setting commands in the instruction stream Apr 5, 1999 Issued
Array ( [id] => 1604460 [patent_doc_number] => 06434646 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Signal distribution system and method based on bus arrangement' [patent_app_type] => B1 [patent_app_number] => 09/287490 [patent_app_country] => US [patent_app_date] => 1999-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 70 [patent_no_of_words] => 5491 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434646.pdf [firstpage_image] =>[orig_patent_app_number] => 09287490 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/287490
Signal distribution system and method based on bus arrangement Apr 5, 1999 Issued
Array ( [id] => 4388893 [patent_doc_number] => 06275947 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Control circuit and method to wake up or turn on computer via peripheral device' [patent_app_type] => 1 [patent_app_number] => 9/286141 [patent_app_country] => US [patent_app_date] => 1999-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2859 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275947.pdf [firstpage_image] =>[orig_patent_app_number] => 286141 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/286141
Control circuit and method to wake up or turn on computer via peripheral device Apr 4, 1999 Issued
Array ( [id] => 1395072 [patent_doc_number] => 06567875 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'USB data serializer' [patent_app_type] => B1 [patent_app_number] => 09/286044 [patent_app_country] => US [patent_app_date] => 1999-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4845 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567875.pdf [firstpage_image] =>[orig_patent_app_number] => 09286044 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/286044
USB data serializer Apr 4, 1999 Issued
Array ( [id] => 4424678 [patent_doc_number] => 06230228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Efficient bridge architecture for handling multiple write transactions simultaneously' [patent_app_type] => 1 [patent_app_number] => 9/283929 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3903 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230228.pdf [firstpage_image] =>[orig_patent_app_number] => 283929 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283929
Efficient bridge architecture for handling multiple write transactions simultaneously Mar 31, 1999 Issued
Array ( [id] => 1471896 [patent_doc_number] => 06460108 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Low cost data streaming mechanism' [patent_app_type] => B1 [patent_app_number] => 09/282386 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4869 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460108.pdf [firstpage_image] =>[orig_patent_app_number] => 09282386 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282386
Low cost data streaming mechanism Mar 30, 1999 Issued
Array ( [id] => 4292770 [patent_doc_number] => 06247134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Method and system for pipe stage gating within an operating pipelined circuit for power savings' [patent_app_type] => 1 [patent_app_number] => 9/283128 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7922 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247134.pdf [firstpage_image] =>[orig_patent_app_number] => 283128 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283128
Method and system for pipe stage gating within an operating pipelined circuit for power savings Mar 30, 1999 Issued
Array ( [id] => 1484923 [patent_doc_number] => 06453374 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Data bus' [patent_app_type] => B1 [patent_app_number] => 09/281584 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5512 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453374.pdf [firstpage_image] =>[orig_patent_app_number] => 09281584 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/281584
Data bus Mar 29, 1999 Issued
Array ( [id] => 4424386 [patent_doc_number] => 06266722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Multi-value logic device, bus system of multi-value logic devices connected with shared bus, and network system of information processors loaded with multi-value logic devices and connected with shared network' [patent_app_type] => 1 [patent_app_number] => 9/277847 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7145 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266722.pdf [firstpage_image] =>[orig_patent_app_number] => 277847 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/277847
Multi-value logic device, bus system of multi-value logic devices connected with shared bus, and network system of information processors loaded with multi-value logic devices and connected with shared network Mar 28, 1999 Issued
Array ( [id] => 4424395 [patent_doc_number] => 06266723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Method and system for optimizing of peripheral component interconnect PCI bus transfers' [patent_app_type] => 1 [patent_app_number] => 9/280093 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 12429 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266723.pdf [firstpage_image] =>[orig_patent_app_number] => 280093 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/280093
Method and system for optimizing of peripheral component interconnect PCI bus transfers Mar 28, 1999 Issued
Array ( [id] => 6413834 [patent_doc_number] => 20020038398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'MECHANISM FOR IMPLEMENTING BUS LOCKING WITH A MIXED ARCHITECTURE' [patent_app_type] => new [patent_app_number] => 09/277718 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20020038398.pdf [firstpage_image] =>[orig_patent_app_number] => 09277718 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/277718
Mechanism for implementing bus locking with a mixed architecture Mar 25, 1999 Issued
Array ( [id] => 4333615 [patent_doc_number] => 06317840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Control of multiple equivalent functional units for power reduction' [patent_app_type] => 1 [patent_app_number] => 9/275170 [patent_app_country] => US [patent_app_date] => 1999-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2659 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317840.pdf [firstpage_image] =>[orig_patent_app_number] => 275170 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/275170
Control of multiple equivalent functional units for power reduction Mar 23, 1999 Issued
Array ( [id] => 1521678 [patent_doc_number] => 06502157 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Method and system for perfetching data in a bridge system' [patent_app_type] => B1 [patent_app_number] => 09/275857 [patent_app_country] => US [patent_app_date] => 1999-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13471 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502157.pdf [firstpage_image] =>[orig_patent_app_number] => 09275857 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/275857
Method and system for perfetching data in a bridge system Mar 23, 1999 Issued
Array ( [id] => 4349354 [patent_doc_number] => 06321283 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method and apparatus for determining a data transmission capacity between communicatively connected source and target devices' [patent_app_type] => 1 [patent_app_number] => 9/274026 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7507 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321283.pdf [firstpage_image] =>[orig_patent_app_number] => 274026 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/274026
Method and apparatus for determining a data transmission capacity between communicatively connected source and target devices Mar 21, 1999 Issued
Array ( [id] => 4351647 [patent_doc_number] => 06314482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Method and system for indexing adapters within a data processing system' [patent_app_type] => 1 [patent_app_number] => 9/273208 [patent_app_country] => US [patent_app_date] => 1999-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2858 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314482.pdf [firstpage_image] =>[orig_patent_app_number] => 273208 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/273208
Method and system for indexing adapters within a data processing system Mar 18, 1999 Issued
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