Search

Xuan Marian Thai

Examiner (ID: 451)

Most Active Art Unit
3715
Art Unit(s)
2781, 3714, 3713, 3403, 3715, 2181, 2111, 2782
Total Applications
775
Issued Applications
391
Pending Applications
172
Abandoned Applications
214

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7645924 [patent_doc_number] => 06477599 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Data processing system and microcomputer' [patent_app_type] => B1 [patent_app_number] => 09/186075 [patent_app_country] => US [patent_app_date] => 1998-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 12866 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477599.pdf [firstpage_image] =>[orig_patent_app_number] => 09186075 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/186075
Data processing system and microcomputer Nov 4, 1998 Issued
Array ( [id] => 4374460 [patent_doc_number] => 06170027 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'LPC/ISA bridge and its bridging method' [patent_app_type] => 1 [patent_app_number] => 9/186956 [patent_app_country] => US [patent_app_date] => 1998-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3308 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170027.pdf [firstpage_image] =>[orig_patent_app_number] => 186956 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/186956
LPC/ISA bridge and its bridging method Nov 4, 1998 Issued
Array ( [id] => 4380788 [patent_doc_number] => 06256681 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Data buffer for programmable memory' [patent_app_type] => 1 [patent_app_number] => 9/185088 [patent_app_country] => US [patent_app_date] => 1998-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256681.pdf [firstpage_image] =>[orig_patent_app_number] => 185088 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/185088
Data buffer for programmable memory Nov 2, 1998 Issued
Array ( [id] => 4399870 [patent_doc_number] => 06304919 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Fixed frame for a drawout electrical switch' [patent_app_type] => 1 [patent_app_number] => 9/184118 [patent_app_country] => US [patent_app_date] => 1998-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1733 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304919.pdf [firstpage_image] =>[orig_patent_app_number] => 184118 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/184118
Fixed frame for a drawout electrical switch Nov 1, 1998 Issued
Array ( [id] => 4122452 [patent_doc_number] => 06052791 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Control method for a hard disk drive and a data processor reducing power consumption of the hard disk drive' [patent_app_type] => 1 [patent_app_number] => 9/172039 [patent_app_country] => US [patent_app_date] => 1998-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7360 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052791.pdf [firstpage_image] =>[orig_patent_app_number] => 172039 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/172039
Control method for a hard disk drive and a data processor reducing power consumption of the hard disk drive Oct 13, 1998 Issued
Array ( [id] => 4324423 [patent_doc_number] => 06327634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'System and method for compressing and decompressing configuration data for an FPGA' [patent_app_type] => 1 [patent_app_number] => 9/139529 [patent_app_country] => US [patent_app_date] => 1998-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3782 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327634.pdf [firstpage_image] =>[orig_patent_app_number] => 139529 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/139529
System and method for compressing and decompressing configuration data for an FPGA Aug 24, 1998 Issued
Array ( [id] => 4351696 [patent_doc_number] => 06314484 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Computer system with a bus having a segmented structure' [patent_app_type] => 1 [patent_app_number] => 9/112520 [patent_app_country] => US [patent_app_date] => 1998-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6558 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314484.pdf [firstpage_image] =>[orig_patent_app_number] => 112520 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/112520
Computer system with a bus having a segmented structure Jul 8, 1998 Issued
Array ( [id] => 4223615 [patent_doc_number] => 06078976 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Bridge device that prevents decrease in the data transfer efficiency of buses' [patent_app_type] => 1 [patent_app_number] => 9/102685 [patent_app_country] => US [patent_app_date] => 1998-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11949 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078976.pdf [firstpage_image] =>[orig_patent_app_number] => 102685 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/102685
Bridge device that prevents decrease in the data transfer efficiency of buses Jun 22, 1998 Issued
Array ( [id] => 4151419 [patent_doc_number] => 06035353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Computer including data signal monitoring circuit' [patent_app_type] => 1 [patent_app_number] => 9/087498 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2839 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035353.pdf [firstpage_image] =>[orig_patent_app_number] => 087498 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/087498
Computer including data signal monitoring circuit May 28, 1998 Issued
Array ( [id] => 4114336 [patent_doc_number] => 06049841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Method and apparatus of selecting data transmission channels' [patent_app_type] => 1 [patent_app_number] => 9/085196 [patent_app_country] => US [patent_app_date] => 1998-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9989 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049841.pdf [firstpage_image] =>[orig_patent_app_number] => 085196 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/085196
Method and apparatus of selecting data transmission channels May 26, 1998 Issued
Array ( [id] => 4100793 [patent_doc_number] => 06018780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Method and apparatus for downloading a file to a remote unit' [patent_app_type] => 1 [patent_app_number] => 9/081192 [patent_app_country] => US [patent_app_date] => 1998-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2951 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018780.pdf [firstpage_image] =>[orig_patent_app_number] => 081192 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/081192
Method and apparatus for downloading a file to a remote unit May 18, 1998 Issued
Array ( [id] => 4132971 [patent_doc_number] => 06047345 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment' [patent_app_type] => 1 [patent_app_number] => 9/078713 [patent_app_country] => US [patent_app_date] => 1998-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5214 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/047/06047345.pdf [firstpage_image] =>[orig_patent_app_number] => 078713 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/078713
Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment May 13, 1998 Issued
Array ( [id] => 4036773 [patent_doc_number] => 05968156 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Programmable peripheral component interconnect (PCI) bridge for interfacing a PCI bus and a local bus having reconstructable interface logic circuit therein' [patent_app_type] => 1 [patent_app_number] => 9/063428 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2383 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968156.pdf [firstpage_image] =>[orig_patent_app_number] => 063428 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063428
Programmable peripheral component interconnect (PCI) bridge for interfacing a PCI bus and a local bus having reconstructable interface logic circuit therein Apr 20, 1998 Issued
Array ( [id] => 4195515 [patent_doc_number] => 06085330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Control circuit for switching a processor between multiple low power states to allow cache snoops' [patent_app_type] => 1 [patent_app_number] => 9/056838 [patent_app_country] => US [patent_app_date] => 1998-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3870 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085330.pdf [firstpage_image] =>[orig_patent_app_number] => 056838 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/056838
Control circuit for switching a processor between multiple low power states to allow cache snoops Apr 6, 1998 Issued
Array ( [id] => 4252262 [patent_doc_number] => 06076130 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'System and method for efficient communication between buses' [patent_app_type] => 1 [patent_app_number] => 9/044660 [patent_app_country] => US [patent_app_date] => 1998-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 23 [patent_no_of_words] => 3899 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/076/06076130.pdf [firstpage_image] =>[orig_patent_app_number] => 044660 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/044660
System and method for efficient communication between buses Mar 18, 1998 Issued
Array ( [id] => 3970204 [patent_doc_number] => 05991833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Computer system with bridge logic that reduces interference to CPU cycles during secondary bus transactions' [patent_app_type] => 1 [patent_app_number] => 9/042036 [patent_app_country] => US [patent_app_date] => 1998-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8706 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991833.pdf [firstpage_image] =>[orig_patent_app_number] => 042036 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/042036
Computer system with bridge logic that reduces interference to CPU cycles during secondary bus transactions Mar 12, 1998 Issued
Array ( [id] => 4401924 [patent_doc_number] => 06279061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Data processing apparatus for modifying information data between two interfaces and using control data of one interface to control a second interface' [patent_app_type] => 1 [patent_app_number] => 9/037293 [patent_app_country] => US [patent_app_date] => 1998-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4398 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279061.pdf [firstpage_image] =>[orig_patent_app_number] => 037293 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/037293
Data processing apparatus for modifying information data between two interfaces and using control data of one interface to control a second interface Mar 8, 1998 Issued
Array ( [id] => 4166967 [patent_doc_number] => 06065079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Apparatus for switching a bus power line to a peripheral device to ground in response to a signal indicating single ended configuration of the bus' [patent_app_type] => 1 [patent_app_number] => 9/022186 [patent_app_country] => US [patent_app_date] => 1998-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2022 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065079.pdf [firstpage_image] =>[orig_patent_app_number] => 022186 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/022186
Apparatus for switching a bus power line to a peripheral device to ground in response to a signal indicating single ended configuration of the bus Feb 10, 1998 Issued
Array ( [id] => 4198777 [patent_doc_number] => 06038623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Electronic network allowing multi-speed communication' [patent_app_type] => 1 [patent_app_number] => 9/015882 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 10331 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038623.pdf [firstpage_image] =>[orig_patent_app_number] => 015882 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/015882
Electronic network allowing multi-speed communication Jan 28, 1998 Issued
Array ( [id] => 4088437 [patent_doc_number] => 06070210 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Timing mode selection apparatus for handling both burst mode data and single mode data in a DMA transmission system' [patent_app_type] => 1 [patent_app_number] => 9/005578 [patent_app_country] => US [patent_app_date] => 1998-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1988 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/070/06070210.pdf [firstpage_image] =>[orig_patent_app_number] => 005578 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/005578
Timing mode selection apparatus for handling both burst mode data and single mode data in a DMA transmission system Jan 11, 1998 Issued
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