
Xuong My Chung Trans
Examiner (ID: 10115, Phone: (571)272-2002 , Office: P/2833 )
| Most Active Art Unit | 2833 |
| Art Unit(s) | 2305, 2308, 2181, 2411, 2311, 2781, 2301, 2833 |
| Total Applications | 1450 |
| Issued Applications | 1154 |
| Pending Applications | 43 |
| Abandoned Applications | 257 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1456877
[patent_doc_number] => 06457133
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Automatic transaction apparatus'
[patent_app_type] => B1
[patent_app_number] => 09/348070
[patent_app_country] => US
[patent_app_date] => 1999-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4434
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/457/06457133.pdf
[firstpage_image] =>[orig_patent_app_number] => 09348070
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/348070 | Automatic transaction apparatus | Jul 5, 1999 | Issued |
Array
(
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[patent_doc_number] => 06427181
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[patent_kind] => B1
[patent_issue_date] => 2002-07-30
[patent_title] => 'Method of and apparatus for processing information, and providing medium'
[patent_app_type] => B1
[patent_app_number] => 09/339815
[patent_app_country] => US
[patent_app_date] => 1999-06-25
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[firstpage_image] =>[orig_patent_app_number] => 09339815
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Array
(
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[patent_doc_number] => 06463496
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[patent_kind] => B1
[patent_issue_date] => 2002-10-08
[patent_title] => 'Interface for an I2C bus'
[patent_app_type] => B1
[patent_app_number] => 09/339648
[patent_app_country] => US
[patent_app_date] => 1999-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[firstpage_image] =>[orig_patent_app_number] => 09339648
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/339648 | Interface for an I2C bus | Jun 23, 1999 | Issued |
Array
(
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[patent_doc_number] => 06516367
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-04
[patent_title] => 'Method and system for detecting bus device configuration changes'
[patent_app_type] => B1
[patent_app_number] => 09/339707
[patent_app_country] => US
[patent_app_date] => 1999-06-24
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[pdf_file] => patents/06/516/06516367.pdf
[firstpage_image] =>[orig_patent_app_number] => 09339707
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/339707 | Method and system for detecting bus device configuration changes | Jun 23, 1999 | Issued |
Array
(
[id] => 7642407
[patent_doc_number] => 06430639
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[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Minimizing use of bus command code points to request the start and end of a lock'
[patent_app_type] => B1
[patent_app_number] => 09/339351
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[patent_app_date] => 1999-06-23
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Array
(
[id] => 1462378
[patent_doc_number] => 06427180
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-30
[patent_title] => 'Queued port data controller for microprocessor-based engine control applications'
[patent_app_type] => B1
[patent_app_number] => 09/337799
[patent_app_country] => US
[patent_app_date] => 1999-06-22
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/427/06427180.pdf
[firstpage_image] =>[orig_patent_app_number] => 09337799
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/337799 | Queued port data controller for microprocessor-based engine control applications | Jun 21, 1999 | Issued |
Array
(
[id] => 1513216
[patent_doc_number] => 06442641
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-27
[patent_title] => 'Handling multiple delayed write transactions simultaneously through a bridge'
[patent_app_type] => B1
[patent_app_number] => 09/327986
[patent_app_country] => US
[patent_app_date] => 1999-06-08
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/442/06442641.pdf
[firstpage_image] =>[orig_patent_app_number] => 09327986
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/327986 | Handling multiple delayed write transactions simultaneously through a bridge | Jun 7, 1999 | Issued |
Array
(
[id] => 1318953
[patent_doc_number] => 06618782
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-09
[patent_title] => 'Computer interconnection bus link layer'
[patent_app_type] => B1
[patent_app_number] => 09/326304
[patent_app_country] => US
[patent_app_date] => 1999-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
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[pdf_file] => patents/06/618/06618782.pdf
[firstpage_image] =>[orig_patent_app_number] => 09326304
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/326304 | Computer interconnection bus link layer | Jun 3, 1999 | Issued |
Array
(
[id] => 1505919
[patent_doc_number] => 06487618
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-26
[patent_title] => 'Method for resisting an FPGA interface device'
[patent_app_type] => B1
[patent_app_number] => 09/312316
[patent_app_country] => US
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[patent_drawing_sheets_cnt] => 11
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/487/06487618.pdf
[firstpage_image] =>[orig_patent_app_number] => 09312316
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/312316 | Method for resisting an FPGA interface device | May 13, 1999 | Issued |
Array
(
[id] => 1365068
[patent_doc_number] => 06581125
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-17
[patent_title] => 'PCI bridge having latency inducing serial bus'
[patent_app_type] => B1
[patent_app_number] => 09/312206
[patent_app_country] => US
[patent_app_date] => 1999-05-14
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/581/06581125.pdf
[firstpage_image] =>[orig_patent_app_number] => 09312206
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/312206 | PCI bridge having latency inducing serial bus | May 13, 1999 | Issued |
Array
(
[id] => 1406424
[patent_doc_number] => 06560665
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-06
[patent_title] => 'Embedding firmware for a microprocessor with configuration data for a field programmable gate array'
[patent_app_type] => B1
[patent_app_number] => 09/312282
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[pdf_file] => patents/06/560/06560665.pdf
[firstpage_image] =>[orig_patent_app_number] => 09312282
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/312282 | Embedding firmware for a microprocessor with configuration data for a field programmable gate array | May 13, 1999 | Issued |
Array
(
[id] => 1552735
[patent_doc_number] => 06446147
[patent_country] => US
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[patent_issue_date] => 2002-09-03
[patent_title] => 'Wired-or connection in differential transmission environment'
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[patent_app_number] => 09/311159
[patent_app_country] => US
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[pdf_file] => patents/06/446/06446147.pdf
[firstpage_image] =>[orig_patent_app_number] => 09311159
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/311159 | Wired-or connection in differential transmission environment | May 12, 1999 | Issued |
Array
(
[id] => 7644152
[patent_doc_number] => 06473822
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-29
[patent_title] => 'Digital signal processing apparatus'
[patent_app_type] => B1
[patent_app_number] => 09/309433
[patent_app_country] => US
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[pdf_file] => patents/06/473/06473822.pdf
[firstpage_image] =>[orig_patent_app_number] => 09309433
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/309433 | Digital signal processing apparatus | May 10, 1999 | Issued |
Array
(
[id] => 1431372
[patent_doc_number] => 06519668
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[patent_title] => 'Additional extension device having universal applicability'
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[pdf_file] => patents/06/519/06519668.pdf
[firstpage_image] =>[orig_patent_app_number] => 09309595
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/309595 | Additional extension device having universal applicability | May 10, 1999 | Issued |
Array
(
[id] => 7642405
[patent_doc_number] => 06430641
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[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Methods, arbiters, and computer program products that can improve the performance of a pipelined dual bus data processing system'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/304939 | Methods, arbiters, and computer program products that can improve the performance of a pipelined dual bus data processing system | May 3, 1999 | Issued |
| 09/287110 | MOBILE TERMINAL SLEEP PHASE ASSIGNMENT AND ANNOUNCEMENT IN A WIRELESS LOCAL AREA NETWORK | Apr 6, 1999 | Abandoned |
Array
(
[id] => 4298397
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[patent_issue_date] => 2001-08-28
[patent_title] => 'Multiprocessor data processing system and method of interrupt handling that facilitate identification of a processor requesting a system management interrupt'
[patent_app_type] => 1
[patent_app_number] => 9/282332
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/282332 | Multiprocessor data processing system and method of interrupt handling that facilitate identification of a processor requesting a system management interrupt | Mar 30, 1999 | Issued |
Array
(
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Array
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Array
(
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