Search

Xuong My Chung Trans

Examiner (ID: 10115, Phone: (571)272-2002 , Office: P/2833 )

Most Active Art Unit
2833
Art Unit(s)
2305, 2308, 2181, 2411, 2311, 2781, 2301, 2833
Total Applications
1450
Issued Applications
1154
Pending Applications
43
Abandoned Applications
257

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4372916 [patent_doc_number] => 06169930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Method and apparatus for preventing cold temperature induced damage in a disk drive' [patent_app_type] => 1 [patent_app_number] => 9/062072 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2546 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169930.pdf [firstpage_image] =>[orig_patent_app_number] => 062072 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/062072
Method and apparatus for preventing cold temperature induced damage in a disk drive Apr 16, 1998 Issued
Array ( [id] => 4194787 [patent_doc_number] => 06085279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Interrupt control system provided in a computer' [patent_app_type] => 1 [patent_app_number] => 9/033629 [patent_app_country] => US [patent_app_date] => 1998-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6530 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085279.pdf [firstpage_image] =>[orig_patent_app_number] => 033629 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/033629
Interrupt control system provided in a computer Mar 3, 1998 Issued
Array ( [id] => 4164677 [patent_doc_number] => 06036345 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Design and engineering project management system' [patent_app_type] => 1 [patent_app_number] => 9/027122 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 34 [patent_no_of_words] => 7413 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/036/06036345.pdf [firstpage_image] =>[orig_patent_app_number] => 027122 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/027122
Design and engineering project management system Feb 19, 1998 Issued
Array ( [id] => 4403729 [patent_doc_number] => 06263389 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Apparatus for increasing the number of loads supported by a host bus' [patent_app_type] => 1 [patent_app_number] => 9/009915 [patent_app_country] => US [patent_app_date] => 1998-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4733 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263389.pdf [firstpage_image] =>[orig_patent_app_number] => 009915 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/009915
Apparatus for increasing the number of loads supported by a host bus Jan 20, 1998 Issued
Array ( [id] => 4279510 [patent_doc_number] => 06205501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Apparatus and method for handling universal serial bus control transfers' [patent_app_type] => 1 [patent_app_number] => 9/004002 [patent_app_country] => US [patent_app_date] => 1998-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 9445 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205501.pdf [firstpage_image] =>[orig_patent_app_number] => 004002 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/004002
Apparatus and method for handling universal serial bus control transfers Jan 6, 1998 Issued
Array ( [id] => 1495230 [patent_doc_number] => 06418493 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Method and apparatus for robust addressing on a dynamically configurable bus' [patent_app_type] => B1 [patent_app_number] => 08/998583 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2929 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418493.pdf [firstpage_image] =>[orig_patent_app_number] => 08998583 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/998583
Method and apparatus for robust addressing on a dynamically configurable bus Dec 28, 1997 Issued
Array ( [id] => 4291925 [patent_doc_number] => 06247079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Apparatus for computer implemented hot-swap and hot-add' [patent_app_type] => 1 [patent_app_number] => 8/942282 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 14836 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247079.pdf [firstpage_image] =>[orig_patent_app_number] => 942282 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/942282
Apparatus for computer implemented hot-swap and hot-add Sep 30, 1997 Issued
Array ( [id] => 3755565 [patent_doc_number] => 05787260 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Busline length recognition system' [patent_app_type] => 1 [patent_app_number] => 8/934887 [patent_app_country] => US [patent_app_date] => 1997-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3438 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787260.pdf [firstpage_image] =>[orig_patent_app_number] => 934887 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/934887
Busline length recognition system Sep 21, 1997 Issued
Array ( [id] => 4048270 [patent_doc_number] => 05857116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Circuit for disabling an address masking control signal when a microprocessor is in a system management mode' [patent_app_type] => 1 [patent_app_number] => 8/918838 [patent_app_country] => US [patent_app_date] => 1997-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5160 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/857/05857116.pdf [firstpage_image] =>[orig_patent_app_number] => 918838 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/918838
Circuit for disabling an address masking control signal when a microprocessor is in a system management mode Aug 25, 1997 Issued
Array ( [id] => 3969929 [patent_doc_number] => 05958032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Data processing and communicating system with high throughput peripheral component interconnect bus' [patent_app_type] => 1 [patent_app_number] => 8/895984 [patent_app_country] => US [patent_app_date] => 1997-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3460 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958032.pdf [firstpage_image] =>[orig_patent_app_number] => 895984 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/895984
Data processing and communicating system with high throughput peripheral component interconnect bus Jul 16, 1997 Issued
Array ( [id] => 3997168 [patent_doc_number] => 05961627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'High speed switch for high speed connection between computers and peripheral devices' [patent_app_type] => 1 [patent_app_number] => 8/878081 [patent_app_country] => US [patent_app_date] => 1997-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1050 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/961/05961627.pdf [firstpage_image] =>[orig_patent_app_number] => 878081 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878081
High speed switch for high speed connection between computers and peripheral devices Jun 17, 1997 Issued
Array ( [id] => 4042490 [patent_doc_number] => 05931933 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Apparatus and method for communication and translation for selected one of a variety of data bus formats' [patent_app_type] => 1 [patent_app_number] => 8/877014 [patent_app_country] => US [patent_app_date] => 1997-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1210 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/931/05931933.pdf [firstpage_image] =>[orig_patent_app_number] => 877014 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/877014
Apparatus and method for communication and translation for selected one of a variety of data bus formats Jun 15, 1997 Issued
Array ( [id] => 3915753 [patent_doc_number] => 05944831 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Power management apparatus and method for managing power application to individual circuit cards' [patent_app_type] => 1 [patent_app_number] => 8/874493 [patent_app_country] => US [patent_app_date] => 1997-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3951 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/944/05944831.pdf [firstpage_image] =>[orig_patent_app_number] => 874493 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874493
Power management apparatus and method for managing power application to individual circuit cards Jun 12, 1997 Issued
Array ( [id] => 4042187 [patent_doc_number] => 05903737 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Apparatus and method for serial data communication utilizing general microcomputer' [patent_app_type] => 1 [patent_app_number] => 8/865779 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 2118 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903737.pdf [firstpage_image] =>[orig_patent_app_number] => 865779 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865779
Apparatus and method for serial data communication utilizing general microcomputer May 29, 1997 Issued
Array ( [id] => 3945100 [patent_doc_number] => 05935233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Computer system with a switch interconnector for computer devices' [patent_app_type] => 1 [patent_app_number] => 8/859894 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5740 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/935/05935233.pdf [firstpage_image] =>[orig_patent_app_number] => 859894 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/859894
Computer system with a switch interconnector for computer devices May 20, 1997 Issued
Array ( [id] => 4042706 [patent_doc_number] => 05931949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Expansion port providing system power-down prior to connection of peripheral devices' [patent_app_type] => 1 [patent_app_number] => 8/859833 [patent_app_country] => US [patent_app_date] => 1997-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3655 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/931/05931949.pdf [firstpage_image] =>[orig_patent_app_number] => 859833 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/859833
Expansion port providing system power-down prior to connection of peripheral devices May 15, 1997 Issued
Array ( [id] => 4017906 [patent_doc_number] => 05859989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Apparatus method and system for 64 bit peripheral component interconnect bus using accelerated graphics port logic circuits' [patent_app_type] => 1 [patent_app_number] => 8/855341 [patent_app_country] => US [patent_app_date] => 1997-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6917 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859989.pdf [firstpage_image] =>[orig_patent_app_number] => 855341 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/855341
Apparatus method and system for 64 bit peripheral component interconnect bus using accelerated graphics port logic circuits May 12, 1997 Issued
Array ( [id] => 4047789 [patent_doc_number] => 05857086 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Apparatus method and system for peripheral component interconnect bus using accelerated graphics port logic circuits' [patent_app_type] => 1 [patent_app_number] => 8/855401 [patent_app_country] => US [patent_app_date] => 1997-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6829 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/857/05857086.pdf [firstpage_image] =>[orig_patent_app_number] => 855401 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/855401
Apparatus method and system for peripheral component interconnect bus using accelerated graphics port logic circuits May 12, 1997 Issued
Array ( [id] => 3924127 [patent_doc_number] => 05938769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'CPU escalating adapter with multivoltage and multiple frequency selection' [patent_app_type] => 1 [patent_app_number] => 8/845149 [patent_app_country] => US [patent_app_date] => 1997-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1666 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/938/05938769.pdf [firstpage_image] =>[orig_patent_app_number] => 845149 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/845149
CPU escalating adapter with multivoltage and multiple frequency selection Apr 20, 1997 Issued
Array ( [id] => 4076521 [patent_doc_number] => 05896539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Method and system for controlling access to a shared resource in a data processing system utilizing dynamically-determined weighted pseudo-random priorities' [patent_app_type] => 1 [patent_app_number] => 8/839438 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3504 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896539.pdf [firstpage_image] =>[orig_patent_app_number] => 839438 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839438
Method and system for controlling access to a shared resource in a data processing system utilizing dynamically-determined weighted pseudo-random priorities Apr 13, 1997 Issued
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