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Y My Quach Lee

Examiner (ID: 7363)

Most Active Art Unit
2875
Art Unit(s)
2875, 3406, 2885
Total Applications
2135
Issued Applications
1757
Pending Applications
42
Abandoned Applications
318

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3450403 [patent_doc_number] => 05385868 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'Upward plug process for metal via holes' [patent_app_type] => 1 [patent_app_number] => 8/270668 [patent_app_country] => US [patent_app_date] => 1994-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2284 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/385/05385868.pdf [firstpage_image] =>[orig_patent_app_number] => 270668 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/270668
Upward plug process for metal via holes Jul 4, 1994 Issued
Array ( [id] => 3122097 [patent_doc_number] => 05384274 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-24 [patent_title] => 'Method of making a combined semiconductor device and inductor' [patent_app_type] => 1 [patent_app_number] => 8/241946 [patent_app_country] => US [patent_app_date] => 1994-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1691 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/384/05384274.pdf [firstpage_image] =>[orig_patent_app_number] => 241946 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/241946
Method of making a combined semiconductor device and inductor May 11, 1994 Issued
Array ( [id] => 3111911 [patent_doc_number] => 05395773 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'MOSFET with gate-penetrating halo implant' [patent_app_type] => 1 [patent_app_number] => 8/221338 [patent_app_country] => US [patent_app_date] => 1994-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3798 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/395/05395773.pdf [firstpage_image] =>[orig_patent_app_number] => 221338 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/221338
MOSFET with gate-penetrating halo implant Mar 30, 1994 Issued
Array ( [id] => 3460119 [patent_doc_number] => 05391519 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Method for increasing pad bonding of an IC (1)' [patent_app_type] => 1 [patent_app_number] => 8/164342 [patent_app_country] => US [patent_app_date] => 1993-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1321 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/391/05391519.pdf [firstpage_image] =>[orig_patent_app_number] => 164342 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/164342
Method for increasing pad bonding of an IC (1) Dec 8, 1993 Issued
Array ( [id] => 3478553 [patent_doc_number] => 05399533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'Method improving integrated circuit planarization during etchback' [patent_app_type] => 1 [patent_app_number] => 8/161642 [patent_app_country] => US [patent_app_date] => 1993-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3201 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/399/05399533.pdf [firstpage_image] =>[orig_patent_app_number] => 161642 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/161642
Method improving integrated circuit planarization during etchback Nov 30, 1993 Issued
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