Search

Yaima Rigol

Examiner (ID: 7751, Phone: (571)272-1232 , Office: P/2135 )

Most Active Art Unit
2135
Art Unit(s)
2185, 2135
Total Applications
751
Issued Applications
541
Pending Applications
47
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19152588 [patent_doc_number] => 11977499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Streaming transfers and ordering model [patent_app_type] => utility [patent_app_number] => 17/722782 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8700 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722782 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/722782
Streaming transfers and ordering model Apr 17, 2022 Issued
Array ( [id] => 18622466 [patent_doc_number] => 11755509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Deterministic operation of storage class memory [patent_app_type] => utility [patent_app_number] => 17/715404 [patent_app_country] => US [patent_app_date] => 2022-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17715404 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/715404
Deterministic operation of storage class memory Apr 6, 2022 Issued
Array ( [id] => 20159905 [patent_doc_number] => 12386531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Partial block performance management [patent_app_type] => utility [patent_app_number] => 17/713047 [patent_app_country] => US [patent_app_date] => 2022-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17713047 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/713047
Partial block performance management Apr 3, 2022 Issued
Array ( [id] => 17763511 [patent_doc_number] => 20220237123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => APPARATUSES AND METHODS FOR A PROCESSOR ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/712632 [patent_app_country] => US [patent_app_date] => 2022-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 60532 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712632 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712632
Apparatuses and methods for a processor architecture Apr 3, 2022 Issued
Array ( [id] => 20174776 [patent_doc_number] => 12393523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Circuitry and methods for implementing micro-context based trust domains [patent_app_type] => utility [patent_app_number] => 17/709867 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 20727 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709867 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/709867
Circuitry and methods for implementing micro-context based trust domains Mar 30, 2022 Issued
Array ( [id] => 18668544 [patent_doc_number] => 11775444 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-03 [patent_title] => Fetch request arbiter [patent_app_type] => utility [patent_app_number] => 17/694861 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6984 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694861 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694861
Fetch request arbiter Mar 14, 2022 Issued
Array ( [id] => 18781087 [patent_doc_number] => 11822827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Sub-cluster recovery using a partition group index [patent_app_type] => utility [patent_app_number] => 17/694032 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4127 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694032 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694032
Sub-cluster recovery using a partition group index Mar 13, 2022 Issued
Array ( [id] => 18630409 [patent_doc_number] => 20230289302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => MAXIMIZATION OF SPEEDS IN MIXED MEMORY MODULE CONFIGURATIONS [patent_app_type] => utility [patent_app_number] => 17/691365 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17691365 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/691365
MAXIMIZATION OF SPEEDS IN MIXED MEMORY MODULE CONFIGURATIONS Mar 9, 2022 Abandoned
Array ( [id] => 17832129 [patent_doc_number] => 20220269433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => SYSTEM, METHOD AND APPARATUS FOR PEER-TO-PEER COMMUNICATION [patent_app_type] => utility [patent_app_number] => 17/682015 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682015 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/682015
SYSTEM, METHOD AND APPARATUS FOR PEER-TO-PEER COMMUNICATION Feb 27, 2022 Pending
Array ( [id] => 18949952 [patent_doc_number] => 11893248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Secure metadata protection [patent_app_type] => utility [patent_app_number] => 17/670087 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670087 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/670087
Secure metadata protection Feb 10, 2022 Issued
Array ( [id] => 18872966 [patent_doc_number] => 11860773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Memory access statistics monitoring [patent_app_type] => utility [patent_app_number] => 17/591729 [patent_app_country] => US [patent_app_date] => 2022-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7829 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17591729 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/591729
Memory access statistics monitoring Feb 2, 2022 Issued
Array ( [id] => 20883607 [patent_doc_number] => 12699650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-04 [patent_title] => Process for generation of addresses in multi-level data access [patent_app_type] => utility [patent_app_number] => 17/588238 [patent_app_country] => US [patent_app_date] => 2022-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 4024 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588238 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588238
Process for Generation of Addresses in Multi-Level Data Access Jan 28, 2022 Pending
Array ( [id] => 18066954 [patent_doc_number] => 20220398042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => MANAGING ADDRESS ACCESS INFORMATION [patent_app_type] => utility [patent_app_number] => 17/586534 [patent_app_country] => US [patent_app_date] => 2022-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17586534 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/586534
Managing address access information Jan 26, 2022 Issued
Array ( [id] => 19212274 [patent_doc_number] => 12001336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Hybrid parallel programming of single-level cell memory [patent_app_type] => utility [patent_app_number] => 17/585165 [patent_app_country] => US [patent_app_date] => 2022-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17585165 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/585165
Hybrid parallel programming of single-level cell memory Jan 25, 2022 Issued
Array ( [id] => 17597876 [patent_doc_number] => 20220147450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => STORAGE DEDUPLICATION FOR CONTAINERS WITH ENCRYPTED STORAGE [patent_app_type] => utility [patent_app_number] => 17/582524 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13599 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582524 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/582524
Storage deduplication for containers with encrypted storage Jan 23, 2022 Issued
Array ( [id] => 19167214 [patent_doc_number] => 11983119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Namespace mapping structural adjustment in non-volatile memory devices [patent_app_type] => utility [patent_app_number] => 17/569434 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 31 [patent_no_of_words] => 20629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569434 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569434
Namespace mapping structural adjustment in non-volatile memory devices Jan 4, 2022 Issued
Array ( [id] => 17706955 [patent_doc_number] => 20220206961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => ARCHITECTURE, SYSTEM AND METHODS THEREOF FOR SECURE COMPUTING USING HARDWARE SECURITY CLASSIFICATIONS [patent_app_type] => utility [patent_app_number] => 17/646209 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22814 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -37 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17646209 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/646209
Architecture, system and methods thereof for secure computing using hardware security classifications Dec 27, 2021 Issued
Array ( [id] => 18438426 [patent_doc_number] => 20230185721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => ACCUMULATORS CORRESPONDING TO BINS IN MEMORY [patent_app_type] => utility [patent_app_number] => 17/644352 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17644352 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/644352
Accumulators corresponding to bins in memory Dec 14, 2021 Issued
Array ( [id] => 18446051 [patent_doc_number] => 11681622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Dynamic memory address encoding [patent_app_type] => utility [patent_app_number] => 17/551107 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 19725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551107 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/551107
Dynamic memory address encoding Dec 13, 2021 Issued
Array ( [id] => 17659697 [patent_doc_number] => 20220180162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => AI ACCELERATOR, CACHE MEMORY AND METHOD OF OPERATING CACHE MEMORY USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/544224 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544224 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/544224
AI accelerator, cache memory and method of operating cache memory using the same Dec 6, 2021 Issued
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