Search

Yee F. Lam

Examiner (ID: 8477, Phone: (571)270-7577 , Office: P/2465 )

Most Active Art Unit
2465
Art Unit(s)
2465
Total Applications
712
Issued Applications
511
Pending Applications
80
Abandoned Applications
138

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14367029 [patent_doc_number] => 10304827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Process enhancement using double sided epitaxial on substrate [patent_app_type] => utility [patent_app_number] => 15/969296 [patent_app_country] => US [patent_app_date] => 2018-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3793 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15969296 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/969296
Process enhancement using double sided epitaxial on substrate May 1, 2018 Issued
Array ( [id] => 13528297 [patent_doc_number] => 20180315691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/955090 [patent_app_country] => US [patent_app_date] => 2018-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 522 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15955090 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/955090
Semiconductor device Apr 16, 2018 Issued
Array ( [id] => 13970151 [patent_doc_number] => 10214415 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-26 [patent_title] => Hybrid CMOS-MEMS devices adapted for high-temperature operation and method for their manufacture [patent_app_type] => utility [patent_app_number] => 15/910531 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4133 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910531 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/910531
Hybrid CMOS-MEMS devices adapted for high-temperature operation and method for their manufacture Mar 1, 2018 Issued
Array ( [id] => 13740961 [patent_doc_number] => 20180374950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/910448 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910448 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/910448
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Mar 1, 2018 Abandoned
Array ( [id] => 14367305 [patent_doc_number] => 10304967 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-28 [patent_title] => Integration of graphene and boron nitride hetero-structure device over semiconductor layer [patent_app_type] => utility [patent_app_number] => 15/910854 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6622 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910854 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/910854
Integration of graphene and boron nitride hetero-structure device over semiconductor layer Mar 1, 2018 Issued
Array ( [id] => 14079471 [patent_doc_number] => 20190088623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 15/910725 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910725 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/910725
Semiconductor package Mar 1, 2018 Issued
Array ( [id] => 13306803 [patent_doc_number] => 20180204938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => INSULATED GATE BIPOLAR TRANSISTOR AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/874125 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15874125 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/874125
Insulated gate bipolar transistor and fabrication method thereof Jan 17, 2018 Issued
Array ( [id] => 13317523 [patent_doc_number] => 20180210299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/874221 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15874221 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/874221
Display device Jan 17, 2018 Issued
Array ( [id] => 13378805 [patent_doc_number] => 20180240944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => LIGHT EMITTING DEVICE AND IMAGE DISPLAYING SYSTEM [patent_app_type] => utility [patent_app_number] => 15/874019 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11648 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15874019 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/874019
Light emitting device and image displaying system Jan 17, 2018 Issued
Array ( [id] => 14205609 [patent_doc_number] => 10269932 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-23 [patent_title] => Asymmetric formation of epi semiconductor material in source/drain regions of FinFET devices [patent_app_type] => utility [patent_app_number] => 15/874341 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5341 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15874341 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/874341
Asymmetric formation of epi semiconductor material in source/drain regions of FinFET devices Jan 17, 2018 Issued
Array ( [id] => 12693532 [patent_doc_number] => 20180123010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => LIGHT EMITTING DIODE PACKAGE HAVING SERIES CONNECTED LEDS [patent_app_type] => utility [patent_app_number] => 15/853413 [patent_app_country] => US [patent_app_date] => 2017-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15853413 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/853413
Light emitting diode package having series connected LEDs Dec 21, 2017 Issued
Array ( [id] => 12645081 [patent_doc_number] => 20180106858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => DIE TESTING USING TOP SURFACE TEST PADS [patent_app_type] => utility [patent_app_number] => 15/847156 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15847156 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/847156
Test circuitry coupling test pad to functional core input pad Dec 18, 2017 Issued
Array ( [id] => 12849703 [patent_doc_number] => 20180175074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => SEMICONDUCTOR DEVICE, DISPLAY SYSTEM, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 15/837270 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837270 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837270
Semiconductor device, display system, and electronic device Dec 10, 2017 Issued
Array ( [id] => 12918247 [patent_doc_number] => 20180197925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/836927 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15836927 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/836927
Display device Dec 10, 2017 Issued
Array ( [id] => 14367039 [patent_doc_number] => 10304832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-28 [patent_title] => Integrated circuit structure incorporating stacked field effect transistors and method [patent_app_type] => utility [patent_app_number] => 15/814440 [patent_app_country] => US [patent_app_date] => 2017-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 35 [patent_no_of_words] => 12471 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15814440 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/814440
Integrated circuit structure incorporating stacked field effect transistors and method Nov 15, 2017 Issued
Array ( [id] => 13862189 [patent_doc_number] => 10192819 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-29 [patent_title] => Integrated circuit structure incorporating stacked field effect transistors [patent_app_type] => utility [patent_app_number] => 15/814435 [patent_app_country] => US [patent_app_date] => 2017-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 33 [patent_no_of_words] => 12027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15814435 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/814435
Integrated circuit structure incorporating stacked field effect transistors Nov 15, 2017 Issued
Array ( [id] => 13755243 [patent_doc_number] => 10170576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Stable work function for narrow-pitch devices [patent_app_type] => utility [patent_app_number] => 15/813634 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 6058 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813634 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813634
Stable work function for narrow-pitch devices Nov 14, 2017 Issued
Array ( [id] => 14094293 [patent_doc_number] => 10243061 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-26 [patent_title] => Nanosheet transistor [patent_app_type] => utility [patent_app_number] => 15/814376 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 6683 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15814376 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/814376
Nanosheet transistor Nov 14, 2017 Issued
Array ( [id] => 14151623 [patent_doc_number] => 10256201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Bonding pad structure having island portions and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/797956 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4873 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15797956 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/797956
Bonding pad structure having island portions and method for manufacturing the same Oct 29, 2017 Issued
Array ( [id] => 12236262 [patent_doc_number] => 20180069124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'HETEROGENEOUS SOURCE DRAIN REGION AND EXTENSION REGION' [patent_app_type] => utility [patent_app_number] => 15/795445 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15795445 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/795445
Heterogeneous source drain region and extension region Oct 26, 2017 Issued
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