Yelena Rossoshek

Array ( [id] => 14539747 [patent_doc_number] => 20190205495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => METHOD AND SYSTEM FOR FABRICATING UNIQUE CHIPS USING A CHARGED PARTICLE MULTI-BEAMLET LITHOGRAPHY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/331538 [patent_app_country] => US [patent_app_date] => 2017-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16331538 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12705073 [patent_doc_number] => 20180126857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => ELECTRIC VEHICLE POWERED BY CAPACITIVE ENERGY STORAGE MODULES [patent_app_type] => utility [patent_app_number] => 15/675614 [patent_app_country] => US [patent_app_date] => 2017-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17474 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15675614 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16241985 [patent_doc_number] => 20200259219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => COMBINED POWER STORAGE SYSTEM, AND MANAGEMENT SYSTEM THEREFOR [patent_app_type] => utility [patent_app_number] => 16/348168 [patent_app_country] => US [patent_app_date] => 2017-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16348168 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14860183 [patent_doc_number] => 10418834 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Power source apparatus [patent_app_type] => utility [patent_app_number] => 15/655195 [patent_app_country] => US [patent_app_date] => 2017-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5187 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15655195 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12678631 [patent_doc_number] => 20180118043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => Automated Mechanical Parking Structure with Electric Vehicle Charging Device [patent_app_type] => utility [patent_app_number] => 15/655862 [patent_app_country] => US [patent_app_date] => 2017-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15655862 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13521061 [patent_doc_number] => 20180312073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => APPARATUS FOR CONTROLLING BATTERY STATE OF CHARGE, SYSTEM HAVING APPARATUS FOR CONTROLLING BATTERY STATE OF CHARGE, AND METHOD FOR CONTROLLING BATTERY STATE OF CHARGE [patent_app_type] => utility [patent_app_number] => 15/655348 [patent_app_country] => US [patent_app_date] => 2017-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15655348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13630827 [patent_doc_number] => 20180366966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => INTELLIGENT SWITCH SYSTEM AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 15/655842 [patent_app_country] => US [patent_app_date] => 2017-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15655842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12026045 [patent_doc_number] => 20170316145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'ESTIMATION OF CHIP FLOORPLAN ACTIVITY DISTRIBUTION' [patent_app_type] => utility [patent_app_number] => 15/652042 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3716 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15523171 [patent_doc_number] => 10568203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Modifying a circuit design [patent_app_type] => utility [patent_app_number] => 15/615859 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7797 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15615859 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12713821 [patent_doc_number] => 20180129773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => DESIGN METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT LAYOUT AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME [patent_app_type] => utility [patent_app_number] => 15/610751 [patent_app_country] => US [patent_app_date] => 2017-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15610751 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14776767 [patent_doc_number] => 20190263281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => DOCKING STATION FOR MOTORISED VEHICLES [patent_app_type] => utility [patent_app_number] => 16/309873 [patent_app_country] => US [patent_app_date] => 2017-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16309873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12063237 [patent_doc_number] => 20170339581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'HIGH-PERFORMANCE CONTENT RECONSTRUCTION OF MERGED AND REMOVED CELLS IN INTEGRATED CIRCUIT LAYOUT VERIFICATION PROCESS' [patent_app_type] => utility [patent_app_number] => 15/603140 [patent_app_country] => US [patent_app_date] => 2017-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7725 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15603140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14427785 [patent_doc_number] => 10318698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => System and method for assigning color pattern [patent_app_type] => utility [patent_app_number] => 15/595863 [patent_app_country] => US [patent_app_date] => 2017-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7742 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15595863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12986962 [patent_doc_number] => 20170344685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => SCHEMATIC OVERLAY FOR DESIGN AND VERIFICATION [patent_app_type] => utility [patent_app_number] => 15/594142 [patent_app_country] => US [patent_app_date] => 2017-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15594142 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12986971 [patent_doc_number] => 20170344689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => PLACEMENT OF CIRCUIT ELEMENTS IN REGIONS WITH CUSTOMIZED PLACEMENT GRIDS [patent_app_type] => utility [patent_app_number] => 15/593194 [patent_app_country] => US [patent_app_date] => 2017-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15593194 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13556969 [patent_doc_number] => 20180330032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => INDEPENDENTLY PROJECTING A CANONICAL CLOCK [patent_app_type] => utility [patent_app_number] => 15/592351 [patent_app_country] => US [patent_app_date] => 2017-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10813 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15592351 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13556979 [patent_doc_number] => 20180330037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => INTEGRATED CIRCUIT IDENTIFICATION AND REVERSE ENGINEERING [patent_app_type] => utility [patent_app_number] => 15/591691 [patent_app_country] => US [patent_app_date] => 2017-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15591691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15426307 [patent_doc_number] => 10546083 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-28 [patent_title] => System, method, and computer program product for improving coverage accuracy in formal verification [patent_app_type] => utility [patent_app_number] => 15/591293 [patent_app_country] => US [patent_app_date] => 2017-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8957 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15591293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14705129 [patent_doc_number] => 10380314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-13 [patent_title] => System and method for estimating current in an electronic circuit design [patent_app_type] => utility [patent_app_number] => 15/591548 [patent_app_country] => US [patent_app_date] => 2017-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15591548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14736391 [patent_doc_number] => 10387595 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-20 [patent_title] => Systems and methods for modeling integrated clock gates activity for transient vectorless power analysis of an integrated circuit [patent_app_type] => utility [patent_app_number] => 15/590914 [patent_app_country] => US [patent_app_date] => 2017-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15590914 [rel_patent_id] =>[rel_patent_doc_number] =>)