Yelena Rossoshek

Array ( [id] => 15386145 [patent_doc_number] => 10534255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Method of applying vertex based corrections to a semiconductor design [patent_app_type] => utility [patent_app_number] => 15/534921 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 4490 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15534921 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10995259 [patent_doc_number] => 20160192205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'METHOD OF IDENTIFYING REPEATING DESIGN CELLS' [patent_app_type] => utility [patent_app_number] => 14/979127 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2865 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14979127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10826724 [patent_doc_number] => 20160172893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'WIRELESS CHARGING CONTROL METHOD, AND WIRELESS POWER TRANSMISSION APPARATUS AND WIRELESS POWER RECEIVING APPARATUS USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/959535 [patent_app_country] => US [patent_app_date] => 2015-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5444 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14959535 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10818172 [patent_doc_number] => 20160164335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'NON-CONTACT CHARGER' [patent_app_type] => utility [patent_app_number] => 14/959114 [patent_app_country] => US [patent_app_date] => 2015-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7483 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14959114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11669350 [patent_doc_number] => 20170158070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'ENERGY STORAGE DEVICE, EXCHANGE APPARATUS, AND METHOD FOR EXCHANGING AN ENERGY STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/959424 [patent_app_country] => US [patent_app_date] => 2015-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7442 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14959424 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12060368 [patent_doc_number] => 20170336712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'METHOD AND APPARATUS FOR USING PATTERNING DEVICE TOPOGRAPHY INDUCED PHASE' [patent_app_type] => utility [patent_app_number] => 15/528436 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 19251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15528436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11057720 [patent_doc_number] => 20160254682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'SYSTEM AND METHOD FOR TRACKING AND ARCHIVING BATTERY PERFORMANCE DATA' [patent_app_type] => utility [patent_app_number] => 14/949649 [patent_app_country] => US [patent_app_date] => 2015-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15270 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14949649 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12146867 [patent_doc_number] => 09881120 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-30 [patent_title] => 'Method, system, and computer program product for implementing a multi-fabric mixed-signal design spanning across multiple design fabrics with electrical and thermal analysis awareness' [patent_app_type] => utility [patent_app_number] => 14/871735 [patent_app_country] => US [patent_app_date] => 2015-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14405 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14871735 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14556223 [patent_doc_number] => 10346573 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-09 [patent_title] => Method and system for performing incremental post layout simulation with layout edits [patent_app_type] => utility [patent_app_number] => 14/871929 [patent_app_country] => US [patent_app_date] => 2015-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5051 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 448 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14871929 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10991832 [patent_doc_number] => 20160188777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'INTEGRATED CIRCUIT LAYOUT WIRING FOR MULTI-CORE CHIPS' [patent_app_type] => utility [patent_app_number] => 14/871584 [patent_app_country] => US [patent_app_date] => 2015-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9105 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14871584 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10752358 [patent_doc_number] => 20160098509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'INTEGRATED CIRCUIT AND METHOD OF DESIGNING LAYOUT OF INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/868745 [patent_app_country] => US [patent_app_date] => 2015-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 28932 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14868745 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12088452 [patent_doc_number] => 09842183 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-12 [patent_title] => 'Methods and systems for enabling concurrent editing of electronic circuit layouts' [patent_app_type] => utility [patent_app_number] => 14/869505 [patent_app_country] => US [patent_app_date] => 2015-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7349 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14869505 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11352683 [patent_doc_number] => 20160371423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'Process-Induced Asymmetry Detection, Quantification, and Control Using Patterned Wafer Geometry Measurements' [patent_app_type] => utility [patent_app_number] => 14/867226 [patent_app_country] => US [patent_app_date] => 2015-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3441 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14867226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10746476 [patent_doc_number] => 20160092627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'METHOD FOR ORGANIZING, CONTROLLING, AND REPORTING ON DESIGN MISMATCH INFORMATION IN IC PHYSICAL DESIGN DATA' [patent_app_type] => utility [patent_app_number] => 14/868342 [patent_app_country] => US [patent_app_date] => 2015-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7311 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14868342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10674496 [patent_doc_number] => 20160020641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-21 [patent_title] => 'System and method for providing wireless power in a removable wireless charging module' [patent_app_type] => utility [patent_app_number] => 14/868318 [patent_app_country] => US [patent_app_date] => 2015-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14868318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11817096 [patent_doc_number] => 09721048 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-01 [patent_title] => 'Multiprocessing subsystem with FIFO/buffer modes for flexible input/output processing in an emulation system' [patent_app_type] => utility [patent_app_number] => 14/864249 [patent_app_country] => US [patent_app_date] => 2015-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6594 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14864249 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11117265 [patent_doc_number] => 20160314239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'EFFICIENT RESOLUTION OF LATCH RACE CONDITIONS IN EMULATION' [patent_app_type] => utility [patent_app_number] => 14/863843 [patent_app_country] => US [patent_app_date] => 2015-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10177 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14863843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11531387 [patent_doc_number] => 20170091365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'RECTILINEAR MACROS HAVING NON-UNIFORM CHANNEL SPACING' [patent_app_type] => utility [patent_app_number] => 14/864156 [patent_app_country] => US [patent_app_date] => 2015-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7189 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14864156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12114448 [patent_doc_number] => 09870442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-16 [patent_title] => 'Equivalence checking between two or more circuit designs that include square root circuits' [patent_app_type] => utility [patent_app_number] => 14/860549 [patent_app_country] => US [patent_app_date] => 2015-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 8839 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14860549 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12496107 [patent_doc_number] => 09996654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Transistor plasma charging evaluator [patent_app_type] => utility [patent_app_number] => 14/856578 [patent_app_country] => US [patent_app_date] => 2015-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 53 [patent_no_of_words] => 9254 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14856578 [rel_patent_id] =>[rel_patent_doc_number] =>)